From 49fa783914e14949227617d4aa2ec0cce1dd9678 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 29 Sep 2022 10:45:27 -0700 Subject: [PATCH] [script] now suggest to skip pb_pin_fixup step in example scripts for most test cases --- ...behavioral_verilog_example_script.openfpga | 5 +- .../bitstream_setting_example_script.openfpga | 5 +- ...setting_pbPinFixup_example_script.openfpga | 78 +++++++++++++++++++ ...onfiguration_chain_example_script.openfpga | 5 +- ...tom_fabric_netlist_example_script.openfpga | 5 +- ...uplicated_grid_pin_example_script.openfpga | 5 +- .../example_script.openfpga | 5 +- .../example_without_ace_script.openfpga | 5 +- ...fast_configuration_example_script.openfpga | 5 +- .../fix_device_example_script.openfpga | 5 +- ..._bitstream_setting_example_script.openfpga | 5 +- ..._global_tile_clock_example_script.openfpga | 5 +- ..._device_pbPinFixup_example_script.openfpga | 76 ++++++++++++++++++ ...e_route_chan_width_example_script.openfpga | 5 +- ...terogeneous_device_example_script.openfpga | 5 +- ..._device_pbPinFixup_example_script.openfpga | 76 ++++++++++++++++++ .../fix_pins_example_script.openfpga | 5 +- .../flatten_routing_example_script.openfpga | 5 +- ...estbench_bus_group_example_script.openfpga | 5 +- .../full_testbench_example_script.openfpga | 5 +- ...tbench_example_without_ace_script.openfpga | 5 +- ...hout_self_checking_example_script.openfpga | 5 +- ...generate_bitstream_example_script.openfpga | 5 +- ...tstream_fix_device_example_script.openfpga | 5 +- ...al_tile_multiclock_example_script.openfpga | 5 +- ...ticlock_fix_device_example_script.openfpga | 5 +- .../generate_fabric_example_script.openfpga | 2 +- ...enerate_fabric_key_example_script.openfpga | 2 +- ...rate_secure_fabric_example_script.openfpga | 5 +- ...re_fabric_from_key_example_script.openfpga | 5 +- .../generate_spice_example_script.openfpga | 2 +- ...generate_testbench_example_script.openfpga | 5 +- .../global_tile_clock_example_script.openfpga | 5 +- ...ock_full_testbench_example_script.openfpga | 5 +- ...e_clock_pbPinFixup_example_script.openfpga | 77 ++++++++++++++++++ ...al_tile_multiclock_example_script.openfpga | 5 +- ...lobal_nets_on_pins_example_script.openfpga | 5 +- .../implicit_verilog_example_script.openfpga | 5 +- .../iverilog_example_script.openfpga | 5 +- .../iwls_benchmark_example_script.openfpga | 5 +- ...nal_arch_bitstream_example_script.openfpga | 5 +- .../mcnc_example_script.openfpga | 5 +- .../no_time_stamp_example_script.openfpga | 5 +- .../pin_constrain_example_script.openfpga | 5 +- .../preconfig_fabric_example_script.openfpga | 5 +- ...estbench_bus_group_example_script.openfpga | 5 +- ...ench_no_time_stamp_example_script.openfpga | 5 +- ...ench_relative_path_example_script.openfpga | 5 +- ...hout_self_checking_example_script.openfpga | 5 +- .../quicklogic_flow_example_script.openfpga | 5 +- .../openfpga_shell_scripts/rename_scripts.sh | 4 +- ...tream_distribution_example_script.openfpga | 5 +- .../sdc_time_unit_example_script.openfpga | 5 +- .../skywater_tapeout_example_script.openfpga | 5 +- ...g_default_net_type_example_script.openfpga | 5 +- .../vtr_benchmark_example_script.openfpga | 5 +- ...nch_dont_care_bits_example_script.openfpga | 5 +- ...ite_full_testbench_example_script.openfpga | 5 +- ...ench_relative_path_example_script.openfpga | 5 +- .../write_gsb_example_script.openfpga | 5 +- .../write_io_mapping_example_script.openfpga | 5 +- .../global_tile_reset/config/task.conf | 2 +- .../adder/soft_adder/config/task.conf | 2 +- .../multi_mode_mult_16x16/config/task.conf | 2 +- .../dsp/single_mode_mult_8x8/config/task.conf | 2 +- .../config/task.conf | 2 +- .../io/embedded_io/config/task.conf | 2 +- .../fpga_verilog/io/soc_io/config/task.conf | 2 +- .../frac_lut4_arith/config/task.conf | 2 +- .../lut_adder_test/config/task.conf | 2 +- 70 files changed, 374 insertions(+), 226 deletions(-) create mode 100644 openfpga_flow/openfpga_shell_scripts/bitstream_setting_pbPinFixup_example_script.openfpga create mode 100644 openfpga_flow/openfpga_shell_scripts/fix_device_pbPinFixup_example_script.openfpga create mode 100644 openfpga_flow/openfpga_shell_scripts/fix_heterogeneous_device_pbPinFixup_example_script.openfpga create mode 100644 openfpga_flow/openfpga_shell_scripts/global_tile_clock_pbPinFixup_example_script.openfpga diff --git a/openfpga_flow/openfpga_shell_scripts/behavioral_verilog_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/behavioral_verilog_example_script.openfpga index a6c71fbf4..5a1225ece 100644 --- a/openfpga_flow/openfpga_shell_scripts/behavioral_verilog_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/behavioral_verilog_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --skip_sync_clustering_and_routing_results on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -15,9 +15,6 @@ link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edge # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup diff --git a/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga index 8e0c23a53..426c875ff 100644 --- a/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --circuit_format ${OPENFPGA_VPR_CIRCUIT_FORMAT} --skip_sync_clustering_and_routing_results on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --circuit_format ${OPENFPGA_VPR_CIRCUIT_FORMAT} # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -18,9 +18,6 @@ link_openfpga_arch --sort_gsb_chan_node_in_edges # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup diff --git a/openfpga_flow/openfpga_shell_scripts/bitstream_setting_pbPinFixup_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/bitstream_setting_pbPinFixup_example_script.openfpga new file mode 100644 index 000000000..8e0c23a53 --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/bitstream_setting_pbPinFixup_example_script.openfpga @@ -0,0 +1,78 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --circuit_format ${OPENFPGA_VPR_CIRCUIT_FORMAT} --skip_sync_clustering_and_routing_results on + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Read OpenFPGA bitstream settings +read_openfpga_bitstream_setting -f ${OPENFPGA_BITSTREAM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to clustering nets based on routing results +pb_pin_fixup --verbose + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.xml --format xml + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/openfpga_shell_scripts/configuration_chain_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/configuration_chain_example_script.openfpga index 1f882ef6f..9e5575f64 100644 --- a/openfpga_flow/openfpga_shell_scripts/configuration_chain_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/configuration_chain_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --skip_sync_clustering_and_routing_results on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -15,9 +15,6 @@ link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edge # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup diff --git a/openfpga_flow/openfpga_shell_scripts/custom_fabric_netlist_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/custom_fabric_netlist_example_script.openfpga index 66eda926b..f4451b113 100644 --- a/openfpga_flow/openfpga_shell_scripts/custom_fabric_netlist_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/custom_fabric_netlist_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --skip_sync_clustering_and_routing_results on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -15,9 +15,6 @@ link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edge # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup diff --git a/openfpga_flow/openfpga_shell_scripts/duplicated_grid_pin_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/duplicated_grid_pin_example_script.openfpga index 619fc743d..d6e06a9f8 100644 --- a/openfpga_flow/openfpga_shell_scripts/duplicated_grid_pin_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/duplicated_grid_pin_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --skip_sync_clustering_and_routing_results on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -15,9 +15,6 @@ link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edge # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup diff --git a/openfpga_flow/openfpga_shell_scripts/example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/example_script.openfpga index 955d73017..60acf5f98 100644 --- a/openfpga_flow/openfpga_shell_scripts/example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --skip_sync_clustering_and_routing_results on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -15,9 +15,6 @@ link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edge # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup diff --git a/openfpga_flow/openfpga_shell_scripts/example_without_ace_script.openfpga b/openfpga_flow/openfpga_shell_scripts/example_without_ace_script.openfpga index b405930b6..1a096181d 100644 --- a/openfpga_flow/openfpga_shell_scripts/example_without_ace_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/example_without_ace_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --skip_sync_clustering_and_routing_results on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -15,9 +15,6 @@ link_openfpga_arch --sort_gsb_chan_node_in_edges # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup diff --git a/openfpga_flow/openfpga_shell_scripts/fast_configuration_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/fast_configuration_example_script.openfpga index 0b23f6aea..3e48ed015 100644 --- a/openfpga_flow/openfpga_shell_scripts/fast_configuration_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/fast_configuration_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --skip_sync_clustering_and_routing_results on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -15,9 +15,6 @@ link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edge # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup diff --git a/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga index 3b1c1e6cc..5be3a68d5 100644 --- a/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --skip_sync_clustering_and_routing_results on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -15,9 +15,6 @@ link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edge # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup diff --git a/openfpga_flow/openfpga_shell_scripts/fix_device_global_tile_clock_bitstream_setting_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/fix_device_global_tile_clock_bitstream_setting_example_script.openfpga index 5c92873ca..38cf94c26 100644 --- a/openfpga_flow/openfpga_shell_scripts/fix_device_global_tile_clock_bitstream_setting_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/fix_device_global_tile_clock_bitstream_setting_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --skip_sync_clustering_and_routing_results on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE_LAYOUT} # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -18,9 +18,6 @@ link_openfpga_arch --sort_gsb_chan_node_in_edges # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup diff --git a/openfpga_flow/openfpga_shell_scripts/fix_device_global_tile_clock_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/fix_device_global_tile_clock_example_script.openfpga index 7d59cf1d1..7520b35c3 100644 --- a/openfpga_flow/openfpga_shell_scripts/fix_device_global_tile_clock_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/fix_device_global_tile_clock_example_script.openfpga @@ -2,7 +2,7 @@ # When the global clock is defined as a port of a tile, clock routing in VPR should be skipped # This is due to the Fc_in of clock port is set to 0 for global wiring #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --skip_sync_clustering_and_routing_results on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE_LAYOUT} # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -17,9 +17,6 @@ link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edge # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup diff --git a/openfpga_flow/openfpga_shell_scripts/fix_device_pbPinFixup_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/fix_device_pbPinFixup_example_script.openfpga new file mode 100644 index 000000000..3b1c1e6cc --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/fix_device_pbPinFixup_example_script.openfpga @@ -0,0 +1,76 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --skip_sync_clustering_and_routing_results on + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to clustering nets based on routing results +pb_pin_fixup --verbose + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga index 87f88eb0a..ba00c49fe 100644 --- a/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --skip_sync_clustering_and_routing_results on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -15,9 +15,6 @@ link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edge # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup diff --git a/openfpga_flow/openfpga_shell_scripts/fix_heterogeneous_device_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/fix_heterogeneous_device_example_script.openfpga index 0a6501898..c37d9514d 100644 --- a/openfpga_flow/openfpga_shell_scripts/fix_heterogeneous_device_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/fix_heterogeneous_device_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --constant_net_method route --skip_sync_clustering_and_routing_results on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --constant_net_method route # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -15,9 +15,6 @@ link_openfpga_arch --sort_gsb_chan_node_in_edges # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup diff --git a/openfpga_flow/openfpga_shell_scripts/fix_heterogeneous_device_pbPinFixup_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/fix_heterogeneous_device_pbPinFixup_example_script.openfpga new file mode 100644 index 000000000..0a6501898 --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/fix_heterogeneous_device_pbPinFixup_example_script.openfpga @@ -0,0 +1,76 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --constant_net_method route --skip_sync_clustering_and_routing_results on + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to clustering nets based on routing results +pb_pin_fixup --verbose + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --bitstream fabric_bitstream.bit +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/openfpga_shell_scripts/fix_pins_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/fix_pins_example_script.openfpga index 73fd51133..50e520879 100644 --- a/openfpga_flow/openfpga_shell_scripts/fix_pins_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/fix_pins_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --fix_clusters ${OPENFPGA_VPR_FIX_PINS_FILE} --skip_sync_clustering_and_routing_results on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --fix_clusters ${OPENFPGA_VPR_FIX_PINS_FILE} # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -15,9 +15,6 @@ link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edge # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup diff --git a/openfpga_flow/openfpga_shell_scripts/flatten_routing_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/flatten_routing_example_script.openfpga index 7f9e21117..8b82cd93a 100644 --- a/openfpga_flow/openfpga_shell_scripts/flatten_routing_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/flatten_routing_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --skip_sync_clustering_and_routing_results on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -15,9 +15,6 @@ link_openfpga_arch --activity_file ${ACTIVITY_FILE} # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup diff --git a/openfpga_flow/openfpga_shell_scripts/full_testbench_bus_group_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/full_testbench_bus_group_example_script.openfpga index 49a84bb71..530473b76 100644 --- a/openfpga_flow/openfpga_shell_scripts/full_testbench_bus_group_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/full_testbench_bus_group_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --skip_sync_clustering_and_routing_results on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -15,9 +15,6 @@ link_openfpga_arch --sort_gsb_chan_node_in_edges # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup diff --git a/openfpga_flow/openfpga_shell_scripts/full_testbench_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/full_testbench_example_script.openfpga index 9f5701f88..ac0b5e712 100644 --- a/openfpga_flow/openfpga_shell_scripts/full_testbench_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/full_testbench_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --skip_sync_clustering_and_routing_results on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -15,9 +15,6 @@ link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edge # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup diff --git a/openfpga_flow/openfpga_shell_scripts/full_testbench_example_without_ace_script.openfpga b/openfpga_flow/openfpga_shell_scripts/full_testbench_example_without_ace_script.openfpga index 62b10773f..6ecf91d23 100644 --- a/openfpga_flow/openfpga_shell_scripts/full_testbench_example_without_ace_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/full_testbench_example_without_ace_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --skip_sync_clustering_and_routing_results on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -15,9 +15,6 @@ link_openfpga_arch --sort_gsb_chan_node_in_edges # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup diff --git a/openfpga_flow/openfpga_shell_scripts/full_testbench_without_self_checking_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/full_testbench_without_self_checking_example_script.openfpga index 41fcf7e9c..232cacbc0 100644 --- a/openfpga_flow/openfpga_shell_scripts/full_testbench_without_self_checking_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/full_testbench_without_self_checking_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --skip_sync_clustering_and_routing_results on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -15,9 +15,6 @@ link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edge # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup diff --git a/openfpga_flow/openfpga_shell_scripts/generate_bitstream_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/generate_bitstream_example_script.openfpga index dba89a45f..f96daafb9 100644 --- a/openfpga_flow/openfpga_shell_scripts/generate_bitstream_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/generate_bitstream_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --absorb_buffer_luts off --skip_sync_clustering_and_routing_results on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --absorb_buffer_luts off # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -15,9 +15,6 @@ link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edge # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup diff --git a/openfpga_flow/openfpga_shell_scripts/generate_bitstream_fix_device_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/generate_bitstream_fix_device_example_script.openfpga index 3f87fdcca..c0c9ec592 100644 --- a/openfpga_flow/openfpga_shell_scripts/generate_bitstream_fix_device_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/generate_bitstream_fix_device_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --skip_sync_clustering_and_routing_results on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --device ${OPENFPGA_VPR_DEVICE_LAYOUT} # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -15,9 +15,6 @@ link_openfpga_arch --sort_gsb_chan_node_in_edges # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup diff --git a/openfpga_flow/openfpga_shell_scripts/generate_bitstream_global_tile_multiclock_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/generate_bitstream_global_tile_multiclock_example_script.openfpga index 18486c4b9..a8d926cb7 100644 --- a/openfpga_flow/openfpga_shell_scripts/generate_bitstream_global_tile_multiclock_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/generate_bitstream_global_tile_multiclock_example_script.openfpga @@ -2,7 +2,7 @@ # When the global clock is defined as a port of a tile, clock routing in VPR should be skipped # This is due to the Fc_in of clock port is set to 0 for global wiring #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --skip_sync_clustering_and_routing_results on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -21,9 +21,6 @@ link_openfpga_arch --sort_gsb_chan_node_in_edges # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup diff --git a/openfpga_flow/openfpga_shell_scripts/generate_bitstream_global_tile_multiclock_fix_device_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/generate_bitstream_global_tile_multiclock_fix_device_example_script.openfpga index 047445b94..daef2a9f9 100644 --- a/openfpga_flow/openfpga_shell_scripts/generate_bitstream_global_tile_multiclock_fix_device_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/generate_bitstream_global_tile_multiclock_fix_device_example_script.openfpga @@ -2,7 +2,7 @@ # When the global clock is defined as a port of a tile, clock routing in VPR should be skipped # This is due to the Fc_in of clock port is set to 0 for global wiring #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --skip_sync_clustering_and_routing_results on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --device ${OPENFPGA_VPR_DEVICE_LAYOUT} # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -21,9 +21,6 @@ link_openfpga_arch --sort_gsb_chan_node_in_edges # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup diff --git a/openfpga_flow/openfpga_shell_scripts/generate_fabric_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/generate_fabric_example_script.openfpga index ef2d6b440..680ec13f2 100644 --- a/openfpga_flow/openfpga_shell_scripts/generate_fabric_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/generate_fabric_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --skip_sync_clustering_and_routing_results on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} diff --git a/openfpga_flow/openfpga_shell_scripts/generate_fabric_key_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/generate_fabric_key_example_script.openfpga index 72a10b3fc..a836b02bc 100644 --- a/openfpga_flow/openfpga_shell_scripts/generate_fabric_key_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/generate_fabric_key_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --skip_sync_clustering_and_routing_results on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} diff --git a/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_example_script.openfpga index 8a95b4df1..db68cbea4 100644 --- a/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --skip_sync_clustering_and_routing_results on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -15,9 +15,6 @@ link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edge # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup diff --git a/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_from_key_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_from_key_example_script.openfpga index e6e7c138e..bb349c57d 100644 --- a/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_from_key_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_from_key_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --skip_sync_clustering_and_routing_results on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -15,9 +15,6 @@ link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edge # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup diff --git a/openfpga_flow/openfpga_shell_scripts/generate_spice_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/generate_spice_example_script.openfpga index 1d4f5d035..3b50edbc8 100644 --- a/openfpga_flow/openfpga_shell_scripts/generate_spice_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/generate_spice_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --skip_sync_clustering_and_routing_results on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} diff --git a/openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga index e18976ed6..058109b9e 100644 --- a/openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --skip_sync_clustering_and_routing_results on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -15,9 +15,6 @@ link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edge # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup diff --git a/openfpga_flow/openfpga_shell_scripts/global_tile_clock_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/global_tile_clock_example_script.openfpga index 8b1afa26a..cde123acc 100644 --- a/openfpga_flow/openfpga_shell_scripts/global_tile_clock_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/global_tile_clock_example_script.openfpga @@ -2,7 +2,7 @@ # When the global clock is defined as a port of a tile, clock routing in VPR should be skipped # This is due to the Fc_in of clock port is set to 0 for global wiring #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --skip_sync_clustering_and_routing_results on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -17,9 +17,6 @@ link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edge # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup diff --git a/openfpga_flow/openfpga_shell_scripts/global_tile_clock_full_testbench_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/global_tile_clock_full_testbench_example_script.openfpga index 243f3082f..0a125fa5f 100644 --- a/openfpga_flow/openfpga_shell_scripts/global_tile_clock_full_testbench_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/global_tile_clock_full_testbench_example_script.openfpga @@ -2,7 +2,7 @@ # When the global clock is defined as a port of a tile, clock routing in VPR should be skipped # This is due to the Fc_in of clock port is set to 0 for global wiring #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --skip_sync_clustering_and_routing_results on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE_LAYOUT} # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -17,9 +17,6 @@ link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edge # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup diff --git a/openfpga_flow/openfpga_shell_scripts/global_tile_clock_pbPinFixup_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/global_tile_clock_pbPinFixup_example_script.openfpga new file mode 100644 index 000000000..8b1afa26a --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/global_tile_clock_pbPinFixup_example_script.openfpga @@ -0,0 +1,77 @@ +# Run VPR for the 'and' design +# When the global clock is defined as a port of a tile, clock routing in VPR should be skipped +# This is due to the Fc_in of clock port is set to 0 for global wiring +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --skip_sync_clustering_and_routing_results on + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to clustering nets based on routing results +pb_pin_fixup --verbose + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/openfpga_shell_scripts/global_tile_multiclock_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/global_tile_multiclock_example_script.openfpga index 73cdf6c6e..629c70129 100644 --- a/openfpga_flow/openfpga_shell_scripts/global_tile_multiclock_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/global_tile_multiclock_example_script.openfpga @@ -2,7 +2,7 @@ # When the global clock is defined as a port of a tile, clock routing in VPR should be skipped # This is due to the Fc_in of clock port is set to 0 for global wiring #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --skip_sync_clustering_and_routing_results on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -21,9 +21,6 @@ link_openfpga_arch --sort_gsb_chan_node_in_edges # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup diff --git a/openfpga_flow/openfpga_shell_scripts/ignore_global_nets_on_pins_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/ignore_global_nets_on_pins_example_script.openfpga index b5ab53d90..9fff5a5d9 100644 --- a/openfpga_flow/openfpga_shell_scripts/ignore_global_nets_on_pins_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/ignore_global_nets_on_pins_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --skip_sync_clustering_and_routing_results on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -15,9 +15,6 @@ link_openfpga_arch --sort_gsb_chan_node_in_edges # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup diff --git a/openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga index f46760eeb..09e17db50 100644 --- a/openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --skip_sync_clustering_and_routing_results on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -15,9 +15,6 @@ link_openfpga_arch --sort_gsb_chan_node_in_edges # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup diff --git a/openfpga_flow/openfpga_shell_scripts/iverilog_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/iverilog_example_script.openfpga index 0bf12350c..a9c3ed28e 100644 --- a/openfpga_flow/openfpga_shell_scripts/iverilog_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/iverilog_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --absorb_buffer_luts off --skip_sync_clustering_and_routing_results on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --absorb_buffer_luts off # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -15,9 +15,6 @@ link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edge # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup diff --git a/openfpga_flow/openfpga_shell_scripts/iwls_benchmark_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/iwls_benchmark_example_script.openfpga index efc236159..0f77057a0 100644 --- a/openfpga_flow/openfpga_shell_scripts/iwls_benchmark_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/iwls_benchmark_example_script.openfpga @@ -3,7 +3,7 @@ # This is due to the Fc_in of clock port is set to 0 for global wiring # The constant net such as logic '0' and logic '1' must be routed because current architecture cannot produce them locally # Enable block usage in log file, otherwise QoR check in OpenFPGA flow-run will fail -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --route_chan_width ${VPR_ROUTE_CHAN_WIDTH} --constant_net_method route --skip_sync_clustering_and_routing_results on --write_block_usage ${OPENFPGA_VPR_PACK_STATS_FILE} +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --route_chan_width ${VPR_ROUTE_CHAN_WIDTH} --constant_net_method route --write_block_usage ${OPENFPGA_VPR_PACK_STATS_FILE} # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -22,9 +22,6 @@ link_openfpga_arch --sort_gsb_chan_node_in_edges # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup #--verbose - # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup diff --git a/openfpga_flow/openfpga_shell_scripts/load_external_arch_bitstream_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/load_external_arch_bitstream_example_script.openfpga index fd296d24e..e7dfb6436 100644 --- a/openfpga_flow/openfpga_shell_scripts/load_external_arch_bitstream_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/load_external_arch_bitstream_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --fix_clusters ${OPENFPGA_VPR_FIX_CLUSTERS} --skip_sync_clustering_and_routing_results on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --fix_clusters ${OPENFPGA_VPR_FIX_CLUSTERS} # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -15,9 +15,6 @@ link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edge # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup diff --git a/openfpga_flow/openfpga_shell_scripts/mcnc_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/mcnc_example_script.openfpga index 99468e53d..208e8f1a3 100644 --- a/openfpga_flow/openfpga_shell_scripts/mcnc_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/mcnc_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --absorb_buffer_luts off --skip_sync_clustering_and_routing_results on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --absorb_buffer_luts off # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -15,9 +15,6 @@ link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edge # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup diff --git a/openfpga_flow/openfpga_shell_scripts/no_time_stamp_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/no_time_stamp_example_script.openfpga index 43f488eb5..ba0553733 100644 --- a/openfpga_flow/openfpga_shell_scripts/no_time_stamp_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/no_time_stamp_example_script.openfpga @@ -2,7 +2,7 @@ # This script is designed to test the option --no_time_stamp in related commands # It can NOT be used an example script to achieve other objectives #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --clock_modeling route --skip_sync_clustering_and_routing_results on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --clock_modeling route # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -17,9 +17,6 @@ link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edge # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup diff --git a/openfpga_flow/openfpga_shell_scripts/pin_constrain_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/pin_constrain_example_script.openfpga index 5238c8b98..ad29fc51e 100644 --- a/openfpga_flow/openfpga_shell_scripts/pin_constrain_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/pin_constrain_example_script.openfpga @@ -3,7 +3,7 @@ pcf2place --pcf ${OPENFPGA_PCF} --blif ${VPR_TESTBENCH_BLIF} --pin_table ${OPENF # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --fix_clusters ${OPENFPGA_VPR_FIX_PINS_FILE} --skip_sync_clustering_and_routing_results on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --fix_clusters ${OPENFPGA_VPR_FIX_PINS_FILE} # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -18,9 +18,6 @@ link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edge # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup diff --git a/openfpga_flow/openfpga_shell_scripts/preconfig_fabric_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/preconfig_fabric_example_script.openfpga index a7756023d..785584d9c 100644 --- a/openfpga_flow/openfpga_shell_scripts/preconfig_fabric_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/preconfig_fabric_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --skip_sync_clustering_and_routing_results on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -15,9 +15,6 @@ link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edge # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup diff --git a/openfpga_flow/openfpga_shell_scripts/preconfigured_testbench_bus_group_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/preconfigured_testbench_bus_group_example_script.openfpga index 4cba77e8f..b9d61662b 100644 --- a/openfpga_flow/openfpga_shell_scripts/preconfigured_testbench_bus_group_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/preconfigured_testbench_bus_group_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --skip_sync_clustering_and_routing_results on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -15,9 +15,6 @@ link_openfpga_arch --sort_gsb_chan_node_in_edges # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup diff --git a/openfpga_flow/openfpga_shell_scripts/preconfigured_testbench_no_time_stamp_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/preconfigured_testbench_no_time_stamp_example_script.openfpga index e1d7acfc9..fcca4c11e 100644 --- a/openfpga_flow/openfpga_shell_scripts/preconfigured_testbench_no_time_stamp_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/preconfigured_testbench_no_time_stamp_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --skip_sync_clustering_and_routing_results on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -15,9 +15,6 @@ link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edge # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup diff --git a/openfpga_flow/openfpga_shell_scripts/preconfigured_testbench_relative_path_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/preconfigured_testbench_relative_path_example_script.openfpga index 4d68e13d0..c7f19fbb1 100644 --- a/openfpga_flow/openfpga_shell_scripts/preconfigured_testbench_relative_path_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/preconfigured_testbench_relative_path_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --skip_sync_clustering_and_routing_results on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -15,9 +15,6 @@ link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edge # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup diff --git a/openfpga_flow/openfpga_shell_scripts/preconfigured_testbench_without_self_checking_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/preconfigured_testbench_without_self_checking_example_script.openfpga index dbdf4327f..407cbf4b0 100644 --- a/openfpga_flow/openfpga_shell_scripts/preconfigured_testbench_without_self_checking_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/preconfigured_testbench_without_self_checking_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --skip_sync_clustering_and_routing_results on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -15,9 +15,6 @@ link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edge # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup diff --git a/openfpga_flow/openfpga_shell_scripts/quicklogic_flow_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/quicklogic_flow_example_script.openfpga index 49dc9db22..6cd1cb027 100644 --- a/openfpga_flow/openfpga_shell_scripts/quicklogic_flow_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/quicklogic_flow_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --circuit_format ${OPENFPGA_VPR_CIRCUIT_FORMAT} --skip_sync_clustering_and_routing_results on --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --circuit_format ${OPENFPGA_VPR_CIRCUIT_FORMAT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -16,9 +16,6 @@ link_openfpga_arch --sort_gsb_chan_node_in_edges # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup diff --git a/openfpga_flow/openfpga_shell_scripts/rename_scripts.sh b/openfpga_flow/openfpga_shell_scripts/rename_scripts.sh index 38c4676ee..5826d94f9 100644 --- a/openfpga_flow/openfpga_shell_scripts/rename_scripts.sh +++ b/openfpga_flow/openfpga_shell_scripts/rename_scripts.sh @@ -1,5 +1,5 @@ # Makefile to batch process openfpga shell scripts -SHELL = bash +#SHELL = bash #foreach i (*.openfpga) # sed -i 's/--include_timing --include_signal_init --support_icarus_simulator/--include_timing/g' $i @@ -16,5 +16,5 @@ SHELL = bash for i in *.openfpga ; \ - do sed -i 's/skip_sync_clustering_and_routing_results off/skip_sync_clustering_and_routing_results on/g' $i; \ + do sed -i 's/skip_sync_clustering_and_routing_results on/skip_sync_clustering_and_routing_results off/g' $i; \ done diff --git a/openfpga_flow/openfpga_shell_scripts/report_bitstream_distribution_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/report_bitstream_distribution_example_script.openfpga index e829418c6..80df986e4 100644 --- a/openfpga_flow/openfpga_shell_scripts/report_bitstream_distribution_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/report_bitstream_distribution_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --absorb_buffer_luts off --skip_sync_clustering_and_routing_results on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --absorb_buffer_luts off # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -15,9 +15,6 @@ link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edge # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup diff --git a/openfpga_flow/openfpga_shell_scripts/sdc_time_unit_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/sdc_time_unit_example_script.openfpga index a4a9735c8..dbb79e86c 100644 --- a/openfpga_flow/openfpga_shell_scripts/sdc_time_unit_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/sdc_time_unit_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --skip_sync_clustering_and_routing_results on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -15,9 +15,6 @@ link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edge # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup diff --git a/openfpga_flow/openfpga_shell_scripts/skywater_tapeout_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/skywater_tapeout_example_script.openfpga index 1c00a71ae..d9766fe24 100644 --- a/openfpga_flow/openfpga_shell_scripts/skywater_tapeout_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/skywater_tapeout_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off --skip_sync_clustering_and_routing_results on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -15,9 +15,6 @@ link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edge # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup diff --git a/openfpga_flow/openfpga_shell_scripts/verilog_default_net_type_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/verilog_default_net_type_example_script.openfpga index 979626412..ddb5e5b55 100644 --- a/openfpga_flow/openfpga_shell_scripts/verilog_default_net_type_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/verilog_default_net_type_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --skip_sync_clustering_and_routing_results on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -15,9 +15,6 @@ link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edge # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup diff --git a/openfpga_flow/openfpga_shell_scripts/vtr_benchmark_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/vtr_benchmark_example_script.openfpga index 4a0f3e62e..cb24da2ac 100644 --- a/openfpga_flow/openfpga_shell_scripts/vtr_benchmark_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/vtr_benchmark_example_script.openfpga @@ -3,7 +3,7 @@ # This is due to the Fc_in of clock port is set to 0 for global wiring # The constant net such as logic '0' and logic '1' must be routed because current architecture cannot produce them locally # Enable block usage in log file, otherwise QoR check in OpenFPGA flow-run will fail -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --route_chan_width ${VPR_ROUTE_CHAN_WIDTH} --constant_net_method route --skip_sync_clustering_and_routing_results on --write_block_usage ${OPENFPGA_VPR_PACK_STATS_FILE} +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --route_chan_width ${VPR_ROUTE_CHAN_WIDTH} --constant_net_method route --write_block_usage ${OPENFPGA_VPR_PACK_STATS_FILE} # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -22,9 +22,6 @@ link_openfpga_arch --sort_gsb_chan_node_in_edges # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup #--verbose - # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup diff --git a/openfpga_flow/openfpga_shell_scripts/write_full_testbench_dont_care_bits_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/write_full_testbench_dont_care_bits_example_script.openfpga index 4ab38d6a8..28867aee9 100644 --- a/openfpga_flow/openfpga_shell_scripts/write_full_testbench_dont_care_bits_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/write_full_testbench_dont_care_bits_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route ${OPENFPGA_VPR_DEVICE_LAYOUT} --skip_sync_clustering_and_routing_results on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route ${OPENFPGA_VPR_DEVICE_LAYOUT} # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -15,9 +15,6 @@ link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edge # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup diff --git a/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga index 0416d3bce..9eec95b23 100644 --- a/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route ${OPENFPGA_VPR_DEVICE_LAYOUT} --skip_sync_clustering_and_routing_results on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route ${OPENFPGA_VPR_DEVICE_LAYOUT} # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -15,9 +15,6 @@ link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edge # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup diff --git a/openfpga_flow/openfpga_shell_scripts/write_full_testbench_relative_path_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/write_full_testbench_relative_path_example_script.openfpga index b7941ab3a..323146b5c 100644 --- a/openfpga_flow/openfpga_shell_scripts/write_full_testbench_relative_path_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/write_full_testbench_relative_path_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route ${OPENFPGA_VPR_DEVICE_LAYOUT} --skip_sync_clustering_and_routing_results on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route ${OPENFPGA_VPR_DEVICE_LAYOUT} # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -15,9 +15,6 @@ link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edge # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup diff --git a/openfpga_flow/openfpga_shell_scripts/write_gsb_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/write_gsb_example_script.openfpga index bb22f0339..9712926da 100644 --- a/openfpga_flow/openfpga_shell_scripts/write_gsb_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/write_gsb_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --skip_sync_clustering_and_routing_results on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -15,9 +15,6 @@ link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edge # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup diff --git a/openfpga_flow/openfpga_shell_scripts/write_io_mapping_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/write_io_mapping_example_script.openfpga index 2eab09e32..684154f58 100644 --- a/openfpga_flow/openfpga_shell_scripts/write_io_mapping_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/write_io_mapping_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --absorb_buffer_luts off --skip_sync_clustering_and_routing_results on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --absorb_buffer_luts off # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -15,9 +15,6 @@ link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edge # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - # Apply fix-up to Look-Up Table truth tables based on packing results lut_truth_table_fixup diff --git a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_reset/config/task.conf b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_reset/config/task.conf index 05fdf5059..a294fdb0c 100644 --- a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_reset/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_reset/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/global_tile_clock_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/global_tile_clock_pbPinFixup_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/task.conf b/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/task.conf index 2be42b84c..f9a518840 100644 --- a/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 1*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/bitstream_setting_pbPinFixup_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml openfpga_bitstream_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/fpga_verilog/adder/soft_adder/config/bitstream_annotation.xml diff --git a/openfpga_flow/tasks/fpga_verilog/dsp/multi_mode_mult_16x16/config/task.conf b/openfpga_flow/tasks/fpga_verilog/dsp/multi_mode_mult_16x16/config/task.conf index 672f2f120..411798a88 100644 --- a/openfpga_flow/tasks/fpga_verilog/dsp/multi_mode_mult_16x16/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/dsp/multi_mode_mult_16x16/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_heterogeneous_device_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_heterogeneous_device_pbPinFixup_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_frac_dsp16_caravel_io_skywater130nm_fdhd_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml # VPR parameter diff --git a/openfpga_flow/tasks/fpga_verilog/dsp/single_mode_mult_8x8/config/task.conf b/openfpga_flow/tasks/fpga_verilog/dsp/single_mode_mult_8x8/config/task.conf index 8954ec3a1..b39da3baa 100644 --- a/openfpga_flow/tasks/fpga_verilog/dsp/single_mode_mult_8x8/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/dsp/single_mode_mult_8x8/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_heterogeneous_device_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_heterogeneous_device_pbPinFixup_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_dsp8_caravel_io_skywater130nm_fdhd_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml # VPR parameter diff --git a/openfpga_flow/tasks/fpga_verilog/dsp/wide_multi_mode_mult_16x16/config/task.conf b/openfpga_flow/tasks/fpga_verilog/dsp/wide_multi_mode_mult_16x16/config/task.conf index 2b3ffa4b2..e50935a0e 100644 --- a/openfpga_flow/tasks/fpga_verilog/dsp/wide_multi_mode_mult_16x16/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/dsp/wide_multi_mode_mult_16x16/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_heterogeneous_device_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_heterogeneous_device_pbPinFixup_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_frac_dsp16_caravel_io_skywater130nm_fdhd_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml # VPR parameter diff --git a/openfpga_flow/tasks/fpga_verilog/io/embedded_io/config/task.conf b/openfpga_flow/tasks/fpga_verilog/io/embedded_io/config/task.conf index 2c6789133..b30f3aee1 100644 --- a/openfpga_flow/tasks/fpga_verilog/io/embedded_io/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/io/embedded_io/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_pbPinFixup_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=2x2 diff --git a/openfpga_flow/tasks/fpga_verilog/io/soc_io/config/task.conf b/openfpga_flow/tasks/fpga_verilog/io/soc_io/config/task.conf index 1480385a0..e1743d6ff 100644 --- a/openfpga_flow/tasks/fpga_verilog/io/soc_io/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/io/soc_io/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_pbPinFixup_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=2x2 diff --git a/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut4_arith/config/task.conf b/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut4_arith/config/task.conf index e855cb3ba..b85842ed2 100644 --- a/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut4_arith/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut4_arith/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 1*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/bitstream_setting_pbPinFixup_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadderSuperLUT_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml openfpga_bitstream_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut4_arith/config/bitstream_annotation.xml diff --git a/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf b/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf index 5f861bd85..efc6d37b9 100644 --- a/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf +++ b/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 1*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/bitstream_setting_pbPinFixup_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadderSuperLUT_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml openfpga_bitstream_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/bitstream_annotation.xml