From 49bfb3223c1651860d0741d996c35635639dd085 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 1 Nov 2019 10:53:47 -0600
Subject: [PATCH] add compact routing to regression test

---
 .travis/script.sh                             |  2 +-
 .../tasks/compact_routing/config/task.conf    | 59 +++++++++++++++++++
 2 files changed, 60 insertions(+), 1 deletion(-)
 create mode 100644 openfpga_flow/tasks/compact_routing/config/task.conf

diff --git a/.travis/script.sh b/.travis/script.sh
index 843189baf..5c70628f4 100755
--- a/.travis/script.sh
+++ b/.travis/script.sh
@@ -18,5 +18,5 @@ end_section "OpenFPGA.build"
 
 start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
 cd -
-python3 openfpga_flow/scripts/run_fpga_task.py single_mode s298 blif_vpr_flow tileable_routing explicit_verilog --maxthreads 4
+python3 openfpga_flow/scripts/run_fpga_task.py single_mode s298 blif_vpr_flow compact_routing tileable_routing explicit_verilog --maxthreads 4
 end_section "OpenFPGA.TaskTun"
diff --git a/openfpga_flow/tasks/compact_routing/config/task.conf b/openfpga_flow/tasks/compact_routing/config/task.conf
new file mode 100644
index 000000000..44334b6bd
--- /dev/null
+++ b/openfpga_flow/tasks/compact_routing/config/task.conf
@@ -0,0 +1,59 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = test_modes
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.v
+bench0_chan_width = 300
+
+#[SCRIPT_PARAM_FIX_ROUTE_CHAN_WIDTH]
+#fix_route_chan_width=300
+#vpr_fpga_verilog_include_icarus_simulator=
+#vpr_fpga_verilog_formal_verification_top_netlist=
+#vpr_fpga_verilog_include_timing=
+#vpr_fpga_verilog_include_signal_init=
+#vpr_fpga_verilog_print_autocheck_top_testbench=
+#vpr_fpga_bitstream_generator=
+#vpr_fpga_verilog_print_user_defined_template=
+#vpr_fpga_verilog_print_report_timing_tcl=
+#vpr_fpga_verilog_print_sdc_pnr=
+#vpr_fpga_verilog_print_sdc_analysis=
+##vpr_fpga_x2p_compact_routing_hierarchy=
+#end_flow_with_test=
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+min_route_chan_width=1.3
+vpr_fpga_verilog_include_icarus_simulator=
+vpr_fpga_verilog_formal_verification_top_netlist=
+vpr_fpga_verilog_include_timing=
+vpr_fpga_verilog_include_signal_init=
+vpr_fpga_verilog_print_autocheck_top_testbench=
+vpr_fpga_bitstream_generator=
+vpr_fpga_verilog_print_user_defined_template=
+vpr_fpga_verilog_print_report_timing_tcl=
+vpr_fpga_verilog_print_sdc_pnr=
+vpr_fpga_verilog_print_sdc_analysis=
+#vpr_fpga_verilog_explicit_mapping=
+vpr_fpga_x2p_compact_routing_hierarchy=
+end_flow_with_test=
+