diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index 9e293a2a9..e5223f0fe 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -151,8 +151,8 @@ jobs:
             build/openfpga/libopenfpga.a
             build/openfpga/openfpga_shell.so
             build/openfpga/openfpga
-            yosys/install/share
-            yosys/install/bin
+            build/yosys/share
+            build/yosys/bin
             openfpga_flow
             openfpga.sh
 
@@ -446,11 +446,11 @@ jobs:
           chmod +x build/vtr-verilog-to-routing/ace2/ace
           chmod +x build/vtr-verilog-to-routing/vpr/vpr
           chmod +x build/openfpga/openfpga
-          chmod +x yosys/install/bin/yosys
-          chmod +x yosys/install/bin/yosys-abc
-          chmod +x yosys/install/bin/yosys-config
-          chmod +x yosys/install/bin/yosys-filterlib
-          chmod +x yosys/install/bin/yosys-smtbmc
+          chmod +x build/yosys/bin/yosys
+          chmod +x build/yosys/bin/yosys-abc
+          chmod +x build/yosys/bin/yosys-config
+          chmod +x build/yosys/bin/yosys-filterlib
+          chmod +x build/yosys/bin/yosys-smtbmc
       - name: ${{matrix.config.name}}_GCC-8_(Ubuntu 20.04)
         shell: bash
         run: source openfpga.sh && source openfpga_flow/regression_test_scripts/${{matrix.config.name}}.sh --debug --show_thread_logs
diff --git a/CMakeLists.txt b/CMakeLists.txt
index 193ac953e..35a2296c7 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -312,14 +312,14 @@ endif()
 
 # we will check if yosys already exist. if not then build it
 if (OPENFPGA_WITH_YOSYS)
-    if(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/yosys/install/bin/yosys)
+    if(EXISTS ${CMAKE_CURRENT_BINARY_DIR}/yosys/bin/yosys)
         message(STATUS "Yosys pre-build exist so skipping it")
     else ()
         # run makefile provided, we pass-on the options to the local make file 
         add_custom_target(
             yosys ALL 
             COMMAND $(MAKE) config-gcc
-            COMMAND $(MAKE) install PREFIX=${CMAKE_CURRENT_SOURCE_DIR}/yosys/install
+            COMMAND $(MAKE) install PREFIX=${CMAKE_CURRENT_BINARY_DIR}/yosys/
             WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/yosys
             COMMENT "Compile Yosys with given Makefile"
         )
@@ -329,9 +329,9 @@ if (OPENFPGA_WITH_YOSYS)
         if (OPENFPGA_WITH_YOSYS_PLUGIN)
             add_custom_target(
                 yosys-plugins ALL
-                COMMAND $(MAKE) install_ql-qlf YOSYS_PATH=${CMAKE_CURRENT_SOURCE_DIR}/yosys/install EXTRA_FLAGS="-DPASS_NAME=synth_ql"
+                COMMAND $(MAKE) install_ql-qlf YOSYS_PATH=${CMAKE_CURRENT_BINARY_DIR}/yosys EXTRA_FLAGS="-DPASS_NAME=synth_ql"
                 WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/yosys-plugins
-                DEPENDS ${CMAKE_CURRENT_SOURCE_DIR}/yosys/install/bin/yosys
+                DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/yosys/bin/yosys
                 COMMENT "Compile Yosys-plugins with given Makefile"
             )
             add_dependencies(yosys-plugins yosys)
diff --git a/docker/Dockerfile.master b/docker/Dockerfile.master
index 50bf7e30f..769f28e1e 100644
--- a/docker/Dockerfile.master
+++ b/docker/Dockerfile.master
@@ -3,8 +3,8 @@ RUN mkdir -p /opt/openfpga
 WORKDIR /opt/openfpga
 COPY . /opt/openfpga
 RUN chmod +x build/vtr-verilog-to-routing/abc/abc build/vtr-verilog-to-routing/ace2/ace build/openfpga/openfpga build/vtr-verilog-to-routing/vpr/vpr
-RUN chmod +x yosys/install/bin/yosys yosys/install/bin/yosys-abc yosys/install/bin/yosys-config yosys/install/bin/yosys-filterlib yosys/install/bin/yosys-smtbmc
-ENV PATH="/opt/openfpga/build/openfpga:/opt/openfpga/yosys/install/bin:${PATH}"
+RUN chmod +x build/yosys/bin/yosys build/yosys/bin/yosys-abc build/yosys/bin/yosys-config build/yosys/bin/yosys-filterlib build/yosys/bin/yosys-smtbmc
+ENV PATH="/opt/openfpga/build/openfpga:/opt/openfpga/build/yosys/bin:${PATH}"
 ENV PATH="/opt/openfpga/build/vtr-verilog-to-routing/ace2:/opt/openfpga/build/vtr-verilog-to-routing/abc:/opt/openfpga/build/vtr-verilog-to-routing/vpr:${PATH}"
 ENV OPENFPGA_PATH="/opt/openfpga"
 
diff --git a/openfpga_flow/misc/fpgaflow_default_tool_path.conf b/openfpga_flow/misc/fpgaflow_default_tool_path.conf
index 9d0c07982..5958d1b6b 100644
--- a/openfpga_flow/misc/fpgaflow_default_tool_path.conf
+++ b/openfpga_flow/misc/fpgaflow_default_tool_path.conf
@@ -1,13 +1,13 @@
 # Standard Configuration Example
 [CAD_TOOLS_PATH]
 openfpga_shell_path = ${PATH:OPENFPGA_PATH}/build/openfpga/openfpga
-yosys_path = ${PATH:OPENFPGA_PATH}/yosys/install/bin/yosys
+yosys_path = ${PATH:OPENFPGA_PATH}/build/yosys/bin/yosys
 misc_dir = ${PATH:OPENFPGA_PATH}/openfpga_flow/misc
 odin2_path = ${PATH:OPENFPGA_PATH}/openfpga_flow/not_used_atm/odin2.exe
-abc_path = ${PATH:OPENFPGA_PATH}/yosys/install/bin/yosys-abc
+abc_path = ${PATH:OPENFPGA_PATH}/build/yosys/bin/yosys-abc
 abc_mccl_path = ${PATH:OPENFPGA_PATH}/build/vtr-verilog-to-routing/abc/abc
-abc_with_bb_support_path = ${PATH:OPENFPGA_PATH}/vtr-verilog-to-routing/abc/abc
-vpr_path = ${PATH:OPENFPGA_PATH}/vtr-verilog-to-routing/vpr/vpr
+abc_with_bb_support_path = ${PATH:OPENFPGA_PATH}/build/vtr-verilog-to-routing/abc/abc
+vpr_path = ${PATH:OPENFPGA_PATH}/build/vtr-verilog-to-routing/vpr/vpr
 ace_path = ${PATH:OPENFPGA_PATH}/build/vtr-verilog-to-routing/ace2/ace
 pro_blif_path = ${PATH:OPENFPGA_PATH}/openfpga_flow/scripts/pro_blif.pl
 iverilog_path = iverilog