From dae3554fd49cebe939a964ba62eca005cc754c71 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 28 Sep 2021 11:27:49 -0700 Subject: [PATCH 1/5] [Test] Add a new test case for QL memory bank with flatten BL/WL buses using WLR signals --- .../config/task.conf | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/full_testbench/ql_memory_bank_flatten_use_wlr/config/task.conf diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/ql_memory_bank_flatten_use_wlr/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/ql_memory_bank_flatten_use_wlr/config/task.conf new file mode 100644 index 000000000..6d474ea5e --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/ql_memory_bank_flatten_use_wlr/config/task.conf @@ -0,0 +1,44 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_qlbankflatten_use_wlr_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration= + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +bench1_top = or2 +bench1_chan_width = 300 + +bench2_top = and2_latch +bench2_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= From 811c898173f0e8a72b01351077fba7b948473f73 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 28 Sep 2021 11:29:45 -0700 Subject: [PATCH 2/5] [Test] Add the QL mem flatten BL/WL with WLR test to basic regression tests --- openfpga_flow/regression_test_scripts/basic_reg_test.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index cc74b9a4a..b9067ce78 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -58,6 +58,7 @@ run-task basic_tests/full_testbench/ql_memory_bank --debug --show_thread_logs run-task basic_tests/full_testbench/ql_memory_bank_use_wlr --debug --show_thread_logs run-task basic_tests/full_testbench/multi_region_ql_memory_bank --debug --show_thread_logs run-task basic_tests/full_testbench/ql_memory_bank_flatten --debug --show_thread_logs +run-task basic_tests/full_testbench/ql_memory_bank_flatten_use_wlr --debug --show_thread_logs echo -e "Testing testbenches without self checking features"; run-task basic_tests/full_testbench/full_testbench_without_self_checking --debug --show_thread_logs From 4aed045cdde64fa37d4f6bb9f5db8540a3dc6395 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 28 Sep 2021 11:34:20 -0700 Subject: [PATCH 3/5] [Arch] Added a new example OpenFPGA architecture which uses WLR signal in ql memory bank with flatten BL/WLs --- .../k4_N4_40nm_qlbankflatten_wlr_openfpga.xml | 202 ++++++++++++++++++ 1 file changed, 202 insertions(+) create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_qlbankflatten_wlr_openfpga.xml diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_qlbankflatten_wlr_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_qlbankflatten_wlr_openfpga.xml new file mode 100644 index 000000000..f786382f0 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_qlbankflatten_wlr_openfpga.xml @@ -0,0 +1,202 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From 4400dae108c2b5df5bcb3086432b20cf2191b47f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 28 Sep 2021 11:40:25 -0700 Subject: [PATCH 4/5] [Test] Bug fix in the wrong arch name --- .../ql_memory_bank_flatten_use_wlr/config/task.conf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/ql_memory_bank_flatten_use_wlr/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/ql_memory_bank_flatten_use_wlr/config/task.conf index 6d474ea5e..04e345775 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/ql_memory_bank_flatten_use_wlr/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/ql_memory_bank_flatten_use_wlr/config/task.conf @@ -17,7 +17,7 @@ fpga_flow=yosys_vpr [OpenFPGA_SHELL] openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_qlbankflatten_use_wlr_openfpga.xml +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_qlbankflatten_wlr_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout= openfpga_fast_configuration= From 0d72e115ace9e79301bd66c600646d1f98770b2d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 28 Sep 2021 11:53:38 -0700 Subject: [PATCH 5/5] [Engine] Bug fix for the undriven WLR nets in top-level modules --- openfpga/src/fabric/build_top_module_memory_bank.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga/src/fabric/build_top_module_memory_bank.cpp b/openfpga/src/fabric/build_top_module_memory_bank.cpp index 63cf7ea77..188efd2f4 100644 --- a/openfpga/src/fabric/build_top_module_memory_bank.cpp +++ b/openfpga/src/fabric/build_top_module_memory_bank.cpp @@ -907,8 +907,8 @@ void add_top_module_ql_memory_bank_sram_ports(ModuleManager& module_manager, /* Optional: If we have WLR port, we should add a read-back port */ if (!circuit_lib.model_ports_by_type(sram_model, CIRCUIT_MODEL_PORT_WLR).empty()) { - BasicPort readback_port(std::string(MEMORY_WLR_PORT_NAME), wl_size); - module_manager.add_port(module_id, readback_port, ModuleManager::MODULE_INPUT_PORT); + BasicPort wlr_port(generate_regional_blwl_port_name(std::string(MEMORY_WLR_PORT_NAME), config_region), wl_size); + module_manager.add_port(module_id, wlr_port, ModuleManager::MODULE_INPUT_PORT); } } break;