From d60d0540da58366eef5792a88a005143fccac1ee Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 24 Jan 2023 14:58:52 -0800 Subject: [PATCH 1/9] [test] adding a new test case to validate the bitstream overloading for DSP blocks --- .../micro_benchmark/mult/mult16/mult16.v | 18 +++++++ .../micro_benchmark/mult/mult8/mult8.v | 18 +++++++ .../misc/ys_tmpl_yosys_vpr_dsp_flow.ys | 2 +- .../config/bitstream_annotation.xml | 4 ++ .../overload_dsp_mode_bit/config/task.conf | 48 +++++++++++++++++++ 5 files changed, 89 insertions(+), 1 deletion(-) create mode 100644 openfpga_flow/benchmarks/micro_benchmark/mult/mult16/mult16.v create mode 100644 openfpga_flow/benchmarks/micro_benchmark/mult/mult8/mult8.v create mode 100644 openfpga_flow/tasks/fpga_bitstream/overload_dsp_mode_bit/config/bitstream_annotation.xml create mode 100644 openfpga_flow/tasks/fpga_bitstream/overload_dsp_mode_bit/config/task.conf diff --git a/openfpga_flow/benchmarks/micro_benchmark/mult/mult16/mult16.v b/openfpga_flow/benchmarks/micro_benchmark/mult/mult16/mult16.v new file mode 100644 index 000000000..56402cc9a --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/mult/mult16/mult16.v @@ -0,0 +1,18 @@ +//------------------------------------------------------- +// Functionality: A 8-bit multiply circuit using macro +// Author: Tarachand Pagarani +//------------------------------------------------------- + +module mult16(a, b, out); +parameter DATA_WIDTH = 16; /* declare a parameter. default required */ +input [DATA_WIDTH - 1 : 0] a, b; +output [2*DATA_WIDTH - 1 : 0] out; + +(* keep *) + mult_16 #(.MODE(1'b0)) DSP ( + .A(a), + .B(b), + .Y(out), + ); + +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/mult/mult8/mult8.v b/openfpga_flow/benchmarks/micro_benchmark/mult/mult8/mult8.v new file mode 100644 index 000000000..77e8a0f44 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/mult/mult8/mult8.v @@ -0,0 +1,18 @@ +//------------------------------------------------------- +// Functionality: A 8-bit multiply circuit using macro +// Author: Tarachand Pagarani +//------------------------------------------------------- + +module mult8(a, b, out); +parameter DATA_WIDTH = 8; /* declare a parameter. default required */ +input [DATA_WIDTH - 1 : 0] a, b; +output [2*DATA_WIDTH - 1 : 0] out; + +(* keep *) + mult_8 #(.MODE(1'b1)) DSP ( + .A(a), + .B(b), + .Y(out), + ); + +endmodule diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys index 8d1cb998e..b97bf6a18 100644 --- a/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys +++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys @@ -94,4 +94,4 @@ stat # Output netlists ######################### opt_clean -purge -write_blif ${OUTPUT_BLIF} +write_blif ${YOSYS_WRITE_BLIF_OPTIONS} ${OUTPUT_BLIF} diff --git a/openfpga_flow/tasks/fpga_bitstream/overload_dsp_mode_bit/config/bitstream_annotation.xml b/openfpga_flow/tasks/fpga_bitstream/overload_dsp_mode_bit/config/bitstream_annotation.xml new file mode 100644 index 000000000..b51adfbd0 --- /dev/null +++ b/openfpga_flow/tasks/fpga_bitstream/overload_dsp_mode_bit/config/bitstream_annotation.xml @@ -0,0 +1,4 @@ + + + + diff --git a/openfpga_flow/tasks/fpga_bitstream/overload_dsp_mode_bit/config/task.conf b/openfpga_flow/tasks/fpga_bitstream/overload_dsp_mode_bit/config/task.conf new file mode 100644 index 000000000..e19b2c8ab --- /dev/null +++ b/openfpga_flow/tasks/fpga_bitstream/overload_dsp_mode_bit/config/task.conf @@ -0,0 +1,48 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_frac_dsp16_caravel_io_skywater130nm_fdhd_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_bitstream_setting_file=${PATH:TASK_DIR}/config/bitstream_annotation.xml +# VPR parameter +openfpga_vpr_device_layout=3x4 + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mult/mult8/mult8.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mult/mult16/mult16.v + +[SYNTHESIS_PARAM] +# Yosys script parameters +bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm_cell_sim.v +bench_yosys_dsp_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm_dsp_map.v +bench_yosys_dsp_map_parameters_common=-D DSP_A_MAXWIDTH=8 -D DSP_B_MAXWIDTH=8 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=mult_8x8 +bench_yosys_write_blif_options = -param +bench_read_verilog_options_common = -nolatches +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys +bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys + +bench0_top = mult8 +bench1_top = mult16 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= From 1d8c1a6803eee82d5995eb3d3889fbd9324e13d1 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 24 Jan 2023 15:17:50 -0800 Subject: [PATCH 2/9] [arch] adding a new arch to validate fracturable dsp --- .../k4_N4_frac_dsp16_40nm_cc_openfpga.xml | 209 +++++++++ .../k4_N4_tileable_frac_dsp16_40nm.xml | 417 ++++++++++++++++++ 2 files changed, 626 insertions(+) create mode 100644 openfpga_flow/openfpga_arch/k4_N4_frac_dsp16_40nm_cc_openfpga.xml create mode 100644 openfpga_flow/vpr_arch/k4_N4_tileable_frac_dsp16_40nm.xml diff --git a/openfpga_flow/openfpga_arch/k4_N4_frac_dsp16_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_frac_dsp16_40nm_cc_openfpga.xml new file mode 100644 index 000000000..4dcc0f92a --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_frac_dsp16_40nm_cc_openfpga.xml @@ -0,0 +1,209 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_frac_dsp16_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_frac_dsp16_40nm.xml new file mode 100644 index 000000000..a6f1fa77e --- /dev/null +++ b/openfpga_flow/vpr_arch/k4_N4_tileable_frac_dsp16_40nm.xml @@ -0,0 +1,417 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + mult_16.a[0:2] mult_16.b[0:2] mult_16.out[0:5] + mult_16.a[3:5] mult_16.b[3:5] mult_16.out[6:10] + mult_16.a[6:7] mult_16.b[6:7] mult_16.out[11:15] + mult_16.a[8:10] mult_16.b[8:10] mult_16.out[16:21] + mult_16.a[11:13] mult_16.b[11:13] mult_16.out[22:26] + mult_16.a[14:15] mult_16.b[14:15] mult_16.out[27:31] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From fec84d76d11de34cbaca5f4238ef58d524e4c0cb Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 24 Jan 2023 15:22:34 -0800 Subject: [PATCH 3/9] [arch] adding tech lib; --- .../k4_N4_frac_dsp16_40nm_cc_openfpga.xml | 4 +- .../k4_N4_tileable_frac_dsp16_40nm_cell_sim.v | 27 ++++++++++++ .../k4_N4_tileable_frac_dsp16_40nm_dsp_map.v | 41 +++++++++++++++++++ .../overload_dsp_mode_bit/config/task.conf | 10 ++--- 4 files changed, 75 insertions(+), 7 deletions(-) create mode 100644 openfpga_flow/openfpga_yosys_techlib/k4_N4_tileable_frac_dsp16_40nm_cell_sim.v create mode 100644 openfpga_flow/openfpga_yosys_techlib/k4_N4_tileable_frac_dsp16_40nm_dsp_map.v diff --git a/openfpga_flow/openfpga_arch/k4_N4_frac_dsp16_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_frac_dsp16_40nm_cc_openfpga.xml index 4dcc0f92a..ffcf9493d 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_frac_dsp16_40nm_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_frac_dsp16_40nm_cc_openfpga.xml @@ -199,8 +199,8 @@ - - + + diff --git a/openfpga_flow/openfpga_yosys_techlib/k4_N4_tileable_frac_dsp16_40nm_cell_sim.v b/openfpga_flow/openfpga_yosys_techlib/k4_N4_tileable_frac_dsp16_40nm_cell_sim.v new file mode 100644 index 000000000..0cd696757 --- /dev/null +++ b/openfpga_flow/openfpga_yosys_techlib/k4_N4_tileable_frac_dsp16_40nm_cell_sim.v @@ -0,0 +1,27 @@ +//----------------------------- +// 8-bit multiplier +//----------------------------- +module mult_8( + input [0:7] A, + input [0:7] B, + output [0:15] Y +); +parameter MODE = 1'b1; + +assign Y = A * B; + +endmodule + +//----------------------------- +// 16-bit multiplier +//----------------------------- +module mult_16( + input [0:15] A, + input [0:15] B, + output [0:31] Y +); +parameter MODE = 1'b0; + +assign Y = A * B; + +endmodule diff --git a/openfpga_flow/openfpga_yosys_techlib/k4_N4_tileable_frac_dsp16_40nm_dsp_map.v b/openfpga_flow/openfpga_yosys_techlib/k4_N4_tileable_frac_dsp16_40nm_dsp_map.v new file mode 100644 index 000000000..86f307f02 --- /dev/null +++ b/openfpga_flow/openfpga_yosys_techlib/k4_N4_tileable_frac_dsp16_40nm_dsp_map.v @@ -0,0 +1,41 @@ +//----------------------------- +// 8-bit multiplier +//----------------------------- +module mult_8x8 ( + input [0:7] A, + input [0:7] B, + output [0:15] Y +); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 0; + parameter B_WIDTH = 0; + parameter Y_WIDTH = 0; + + mult_8 #(.MODE(1'b1)) _TECHMAP_REPLACE_ ( + .A (A), + .B (B), + .Y (Y) ); + +endmodule + +//----------------------------- +// 16-bit multiplier +//----------------------------- +module mult_16x16 ( + input [0:15] A, + input [0:15] B, + output [0:31] Y +); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 0; + parameter B_WIDTH = 0; + parameter Y_WIDTH = 0; + + mult_16 #(.MODE(1'b0)) _TECHMAP_REPLACE_ ( + .A (A), + .B (B), + .Y (Y) ); + +endmodule diff --git a/openfpga_flow/tasks/fpga_bitstream/overload_dsp_mode_bit/config/task.conf b/openfpga_flow/tasks/fpga_bitstream/overload_dsp_mode_bit/config/task.conf index e19b2c8ab..304b94aec 100644 --- a/openfpga_flow/tasks/fpga_bitstream/overload_dsp_mode_bit/config/task.conf +++ b/openfpga_flow/tasks/fpga_bitstream/overload_dsp_mode_bit/config/task.conf @@ -17,14 +17,14 @@ fpga_flow=yosys_vpr [OpenFPGA_SHELL] openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_frac_dsp16_caravel_io_skywater130nm_fdhd_cc_openfpga.xml +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_frac_dsp16_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml openfpga_bitstream_setting_file=${PATH:TASK_DIR}/config/bitstream_annotation.xml # VPR parameter -openfpga_vpr_device_layout=3x4 +openfpga_vpr_circuit_format=eblif [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_frac_dsp16_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mult/mult8/mult8.v @@ -32,8 +32,8 @@ bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mult/mult1 [SYNTHESIS_PARAM] # Yosys script parameters -bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm_cell_sim.v -bench_yosys_dsp_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm_dsp_map.v +bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_N4_tileable_frac_dsp16_40nm_cell_sim.v +bench_yosys_dsp_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_N4_tileable_frac_dsp16_40nm_dsp_map.v bench_yosys_dsp_map_parameters_common=-D DSP_A_MAXWIDTH=8 -D DSP_B_MAXWIDTH=8 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=mult_8x8 bench_yosys_write_blif_options = -param bench_read_verilog_options_common = -nolatches From e7a3b48475f038b741c292326eb2d9cc30fc6c34 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 24 Jan 2023 15:24:17 -0800 Subject: [PATCH 4/9] [arch] comment on the wrong mode bits --- .../openfpga_arch/k4_N4_frac_dsp16_40nm_cc_openfpga.xml | 1 + 1 file changed, 1 insertion(+) diff --git a/openfpga_flow/openfpga_arch/k4_N4_frac_dsp16_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_frac_dsp16_40nm_cc_openfpga.xml index ffcf9493d..9962461bf 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_frac_dsp16_40nm_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_frac_dsp16_40nm_cc_openfpga.xml @@ -199,6 +199,7 @@ + From 499d352cff137886095d40f5284f6c1bf2199372 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 24 Jan 2023 15:39:42 -0800 Subject: [PATCH 5/9] [flow] add yosys rewrite scripts --- ...ys_tmpl_yosys_vpr_dsp_flow_with_rewrite.ys | 43 +++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow_with_rewrite.ys diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow_with_rewrite.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow_with_rewrite.ys new file mode 100644 index 000000000..49c3b0edc --- /dev/null +++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow_with_rewrite.ys @@ -0,0 +1,43 @@ +# Yosys synthesis script for ${TOP_MODULE} +# Read verilog files +read_verilog ${READ_VERILOG_OPTIONS} ${VERILOG_FILES} +read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG} + +# Technology mapping +hierarchy -top ${TOP_MODULE} +proc +techmap -D NO_LUT -map +/adff2dff.v + +# Synthesis +flatten +opt_expr +opt_clean +check +opt -nodffe -nosdff +fsm +opt -nodffe -nosdff +wreduce +peepopt +opt_clean +opt -nodffe -nosdff +memory -nomap +opt_clean +opt -fast -full -nodffe -nosdff +memory_map +opt -full -nodffe -nosdff +techmap +opt -fast -nodffe -nosdff +clean + +clean + +# LUT mapping +abc -lut ${LUT_SIZE} + +# Check +synth -run check + +# Clean and output blif +opt_clean -purge +write_blif rewritten_${OUTPUT_BLIF} +write_verilog ${OUTPUT_VERILOG} From 8174f5379642161d12b3ceb73b91193aae87131a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 24 Jan 2023 15:42:01 -0800 Subject: [PATCH 6/9] [test] deploy new test to fpga bitstream regression --- .../regression_test_scripts/fpga_bitstream_reg_test.sh | 2 ++ .../tasks/fpga_bitstream/overload_dsp_mode_bit/config/task.conf | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/openfpga_flow/regression_test_scripts/fpga_bitstream_reg_test.sh b/openfpga_flow/regression_test_scripts/fpga_bitstream_reg_test.sh index 6df03b3af..585cd3f19 100755 --- a/openfpga_flow/regression_test_scripts/fpga_bitstream_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/fpga_bitstream_reg_test.sh @@ -29,6 +29,8 @@ run-task fpga_bitstream/repack_wire_lut_strong $@ echo -e "Testing overloading default paths for programmable interconnect when generating bitstream"; run-task fpga_bitstream/overload_mux_default_path $@ +echo -e "Testing overloading mode bits for DSP blocks when generating bitstream"; +run-task fpga_bitstream/overload_dsp_mode_bit $@ echo -e "Testing outputting I/O mapping result to file"; run-task fpga_bitstream/write_io_mapping $@ diff --git a/openfpga_flow/tasks/fpga_bitstream/overload_dsp_mode_bit/config/task.conf b/openfpga_flow/tasks/fpga_bitstream/overload_dsp_mode_bit/config/task.conf index 304b94aec..8f56a790d 100644 --- a/openfpga_flow/tasks/fpga_bitstream/overload_dsp_mode_bit/config/task.conf +++ b/openfpga_flow/tasks/fpga_bitstream/overload_dsp_mode_bit/config/task.conf @@ -38,7 +38,7 @@ bench_yosys_dsp_map_parameters_common=-D DSP_A_MAXWIDTH=8 -D DSP_B_MAXWIDTH=8 -D bench_yosys_write_blif_options = -param bench_read_verilog_options_common = -nolatches bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys -bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys +bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys bench0_top = mult8 bench1_top = mult16 From f964c9ed678bc08689de0ec7a811b07413bf86fd Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 24 Jan 2023 15:48:57 -0800 Subject: [PATCH 7/9] [test] debug --- .../tasks/fpga_bitstream/overload_dsp_mode_bit/config/task.conf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/tasks/fpga_bitstream/overload_dsp_mode_bit/config/task.conf b/openfpga_flow/tasks/fpga_bitstream/overload_dsp_mode_bit/config/task.conf index 8f56a790d..f389d287c 100644 --- a/openfpga_flow/tasks/fpga_bitstream/overload_dsp_mode_bit/config/task.conf +++ b/openfpga_flow/tasks/fpga_bitstream/overload_dsp_mode_bit/config/task.conf @@ -35,7 +35,7 @@ bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mult/mult1 bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_N4_tileable_frac_dsp16_40nm_cell_sim.v bench_yosys_dsp_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_N4_tileable_frac_dsp16_40nm_dsp_map.v bench_yosys_dsp_map_parameters_common=-D DSP_A_MAXWIDTH=8 -D DSP_B_MAXWIDTH=8 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=mult_8x8 -bench_yosys_write_blif_options = -param +bench_yosys_write_blif_options_common = -param bench_read_verilog_options_common = -nolatches bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys From d1e951e52ede4a80e313e68d9b031bfe738b98ab Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 24 Jan 2023 17:57:34 -0800 Subject: [PATCH 8/9] [test] debugging --- .../misc/ys_tmpl_yosys_vpr_dsp_flow.ys | 2 +- .../overload_dsp_mode_bit/config/task.conf | 1 - .../k4_N4_tileable_frac_dsp16_40nm.xml | 18 ++++++++++++++++++ 3 files changed, 19 insertions(+), 2 deletions(-) diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys index b97bf6a18..621502032 100644 --- a/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys +++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys @@ -94,4 +94,4 @@ stat # Output netlists ######################### opt_clean -purge -write_blif ${YOSYS_WRITE_BLIF_OPTIONS} ${OUTPUT_BLIF} +write_blif -param ${OUTPUT_BLIF} diff --git a/openfpga_flow/tasks/fpga_bitstream/overload_dsp_mode_bit/config/task.conf b/openfpga_flow/tasks/fpga_bitstream/overload_dsp_mode_bit/config/task.conf index f389d287c..b634ab62c 100644 --- a/openfpga_flow/tasks/fpga_bitstream/overload_dsp_mode_bit/config/task.conf +++ b/openfpga_flow/tasks/fpga_bitstream/overload_dsp_mode_bit/config/task.conf @@ -35,7 +35,6 @@ bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mult/mult1 bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_N4_tileable_frac_dsp16_40nm_cell_sim.v bench_yosys_dsp_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_N4_tileable_frac_dsp16_40nm_dsp_map.v bench_yosys_dsp_map_parameters_common=-D DSP_A_MAXWIDTH=8 -D DSP_B_MAXWIDTH=8 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=mult_8x8 -bench_yosys_write_blif_options_common = -param bench_read_verilog_options_common = -nolatches bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_frac_dsp16_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_frac_dsp16_40nm.xml index a6f1fa77e..ba168fc33 100644 --- a/openfpga_flow/vpr_arch/k4_N4_tileable_frac_dsp16_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_N4_tileable_frac_dsp16_40nm.xml @@ -25,6 +25,24 @@ that describe them. --> + + + + + + + + + + + + + + + + + + From aff81785816e5ca57bef6e15796871ee729e5113 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 24 Jan 2023 18:00:04 -0800 Subject: [PATCH 9/9] [test] fixed remaining bugs --- openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow_with_rewrite.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow_with_rewrite.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow_with_rewrite.ys index 49c3b0edc..c104ec249 100644 --- a/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow_with_rewrite.ys +++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow_with_rewrite.ys @@ -1,7 +1,7 @@ # Yosys synthesis script for ${TOP_MODULE} # Read verilog files read_verilog ${READ_VERILOG_OPTIONS} ${VERILOG_FILES} -read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG} +read_verilog ${READ_VERILOG_OPTIONS} ${YOSYS_CELL_SIM_VERILOG} # Technology mapping hierarchy -top ${TOP_MODULE}