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[Engine] Now repack outputs more info on accepting design constraints

This commit is contained in:
tangxifan 2022-03-20 09:37:22 +08:00
parent d19aaba272
commit 48ec5abed6
1 changed files with 1 additions and 2 deletions
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3
openfpga/src/repack/repack.cpp
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@ -479,8 +479,7 @@ void add_lb_router_nets(LbRouter& lb_router,
constrained_net_name.c_str()); constrained_net_name.c_str());
} else { } else {
VTR_ASSERT_SAFE(false == atom_ctx.nlist.valid_net_id(constrained_atom_net_id)); VTR_ASSERT_SAFE(false == atom_ctx.nlist.valid_net_id(constrained_atom_net_id));
VTR_LOGV(verbose, VTR_LOG("Accept net '%s' to be constrained on pin '%s[%d]' during repacking\n",
"Accept net '%s' to be constrained on pin '%s[%d]' during repacking\n",
constrained_net_name.c_str(), constrained_net_name.c_str(),
source_pb_pin->port->name, source_pb_pin->port->name,
source_pb_pin->pin_number); source_pb_pin->pin_number);