diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga_synthesizable.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga_synthesizable.xml
index 95ccc9e2d..0f09f9d23 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga_synthesizable.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga_synthesizable.xml
@@ -52,7 +52,7 @@
         10e-12
       </delay_matrix>
     </circuit_model>
-    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/tap_buf4.v>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/tap_buf4.v">
       <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
       <device_technology device_model_name="logic"/>
       <port type="input" prefix="in" size="1"/>
@@ -64,7 +64,7 @@
         10e-12
       </delay_matrix>
     </circuit_model>
-    <circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
+    <circuit_model type="gate" name="OR2" prefix="OR2" is_default="true" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/or2.v">
       <design_technology type="cmos" topology="OR"/>
       <device_technology device_model_name="logic"/>
       <input_buffer exist="false"/>
diff --git a/openfpga_flow/openfpga_cell_library/verilog/or2.v b/openfpga_flow/openfpga_cell_library/verilog/or2.v
new file mode 100644
index 000000000..ec93d17f8
--- /dev/null
+++ b/openfpga_flow/openfpga_cell_library/verilog/or2.v
@@ -0,0 +1,31 @@
+// ----- Verilog module for OR2 -----
+module OR2(a,
+           b,
+           out);
+//----- INPUT PORTS -----
+input [0:0] a;
+//----- INPUT PORTS -----
+input [0:0] b;
+//----- OUTPUT PORTS -----
+output [0:0] out;
+
+//----- BEGIN wire-connection ports -----
+//----- END wire-connection ports -----
+
+
+//----- BEGIN Registered ports -----
+//----- END Registered ports -----
+
+// ----- Verilog codes of a 2-input 1-output AND gate -----
+	assign out[0] = a[0] | b[0];
+
+`ifdef ENABLE_TIMING
+// ------ BEGIN Pin-to-pin Timing constraints -----
+	specify
+		(a[0] => out[0]) = (0.01, 0.01);
+		(b[0] => out[0]) = (0.005, 0.005);
+	endspecify
+// ------ END Pin-to-pin Timing constraints -----
+`endif
+endmodule
+// ----- END Verilog module for OR2 -----