[Benchmark] Add pipelined multiplier benchmark to test DSP block with registers

openfpga_flow/benchmarks/micro_benchmark/mult/mult_2_pipelined/mult_2_pipelined.v

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+//-------------------------------------------------------
+//  Functionality: A 2-bit multiply circuit with pipelines
+//  Author:        Xifan Tang
+//-------------------------------------------------------
+
+module mult_2_pipelined(clk, a, b, out);
+parameter DATA_WIDTH = 2;  /* declare a parameter. default required */
+input [DATA_WIDTH - 1 : 0] a, b;
+input clk;
+output [DATA_WIDTH - 1 : 0] out;
+
+reg [DATA_WIDTH - 1 : 0] a_reg;
+reg [DATA_WIDTH - 1 : 0] b_reg;
+reg [DATA_WIDTH - 1 : 0] out_reg;
+
+always @(posedge clk) begin
+  a_reg <= a;
+  b_reg <= b;
+  out_reg <= a_reg * b_reg;
+  out = out_reg;
+end
+
+endmodule
+
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