From 477e5353447987281dda10144c8fcb5242203e2d Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 2 Jul 2021 11:13:03 -0600
Subject: [PATCH] [HDL] Added a multi-mode FF design with configurable
 asynchronous reset

---
 .../openfpga_cell_library/verilog/dff.v       | 33 ++++++++++++++++---
 1 file changed, 28 insertions(+), 5 deletions(-)

diff --git a/openfpga_flow/openfpga_cell_library/verilog/dff.v b/openfpga_flow/openfpga_cell_library/verilog/dff.v
index c3a5e538e..2eb5765c9 100644
--- a/openfpga_flow/openfpga_cell_library/verilog/dff.v
+++ b/openfpga_flow/openfpga_cell_library/verilog/dff.v
@@ -246,9 +246,9 @@ endmodule //End Of Module
 //-----------------------------------------------------
 // Function : A multi-functional D-type flip-flop with 
 //           - asynchronous reset 
-//             which can be switched between active-low and active hight
-//           - asynchronous set which can be switched 
-//             which can be switched between active-low and active hight
+//             which can be switched between active-low and active high
+//           - asynchronous set 
+//             which can be switched between active-low and active high
 //-----------------------------------------------------
 module MULTI_MODE_DFFSRQ (
   input SET, // Set input
@@ -259,8 +259,8 @@ module MULTI_MODE_DFFSRQ (
   input [0:1] mode // mode-selection bits: bit0 for reset polarity; bit1 for set polarity
 );
 
-wire post_set = mode ? ~SET : SET;
-wire post_reset = mode ? ~RST : RST;
+wire post_set = mode[1] ? ~SET : SET;
+wire post_reset = mode[0] ? ~RST : RST;
 
 DFFSRQ FF_CORE (.SET(post_set),
                 .RST(post_rst),
@@ -271,6 +271,29 @@ DFFSRQ FF_CORE (.SET(post_set),
 
 endmodule //End Of Module
 
+//-----------------------------------------------------
+// Function : A multi-functional D-type flip-flop with 
+//           - asynchronous reset 
+//             which can be switched between active-low and active high
+//-----------------------------------------------------
+module MULTI_MODE_DFFRQ (
+  input RST, // Reset input
+  input CK, // Clock Input
+  input D, // Data Input
+  output Q, // Q output
+  input mode // mode-selection bits: bit0 for reset polarity; bit1 for set polarity
+);
+
+wire post_reset = mode ? ~RST : RST;
+
+DFFRQ FF_CORE (.RST(post_rst),
+               .CK(CK),
+               .D(D),
+               .Q(Q)
+               );
+
+endmodule //End Of Module
+
 //-----------------------------------------------------
 // Function    : D-type flip-flop with 
 //               - asynchronous active high reset