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[test] remove abs paths in golden outputs without time stamps

This commit is contained in:
tangxifan 2022-09-06 15:24:43 -07:00
parent 93ab992187
commit 477e2119d7
5 changed files with 77 additions and 77 deletions
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4
openfpga_flow/openfpga_shell_scripts/no_time_stamp_example_script.openfpga
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@ -60,7 +60,7 @@ report_bitstream_distribution --file ${OPENFPGA_OUTPUT_DIR}/bitstream_distributi
# Write the Verilog netlist for FPGA fabric # Write the Verilog netlist for FPGA fabric
# - Enable the use of explicit port mapping in Verilog netlist # - Enable the use of explicit port mapping in Verilog netlist
write_fabric_verilog --file ${OPENFPGA_OUTPUT_DIR} --explicit_port_mapping --include_timing --print_user_defined_template --verbose --no_time_stamp write_fabric_verilog --file ${OPENFPGA_OUTPUT_DIR} --explicit_port_mapping --include_timing --print_user_defined_template --use_relative_path --verbose --no_time_stamp
# Write the Verilog testbench for FPGA fabric # Write the Verilog testbench for FPGA fabric
# - We suggest the use of same output directory as fabric Verilog netlists # - We suggest the use of same output directory as fabric Verilog netlists
@ -69,7 +69,7 @@ write_fabric_verilog --file ${OPENFPGA_OUTPUT_DIR} --explicit_port_mapping --inc
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ${OPENFPGA_OUTPUT_DIR} --explicit_port_mapping --no_time_stamp write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ${OPENFPGA_OUTPUT_DIR} --explicit_port_mapping --no_time_stamp
write_preconfigured_testbench --file ${OPENFPGA_OUTPUT_DIR} --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --no_time_stamp write_preconfigured_testbench --file ${OPENFPGA_OUTPUT_DIR} --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --use_relative_path --explicit_port_mapping --no_time_stamp
# Write the SDC files for PnR backend # Write the SDC files for PnR backend
# - Turn on every options here # - Turn on every options here

6
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_include_netlists.v
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@ -8,9 +8,9 @@
`timescale 1ns / 1ps `timescale 1ns / 1ps
// ------ Include fabric top-level netlists ----- // ------ Include fabric top-level netlists -----
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_netlists.v" `include "fabric_netlists.v"
`include "and2_output_verilog.v" `include "and2_output_verilog.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_top_formal_verification.v" `include "and2_top_formal_verification.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v" `include "and2_formal_random_top_tb.v"

62
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_netlists.v
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@ -8,46 +8,46 @@
`timescale 1ns / 1ps `timescale 1ns / 1ps
// ------ Include defines: preproc flags ----- // ------ Include defines: preproc flags -----
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fpga_defines.v" `include "fpga_defines.v"
// ------ Include user-defined netlists ----- // ------ Include user-defined netlists -----
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/openfpga_cell_library/verilog/dff.v" `include "/home/tangxifan/test/OpenFPGA/openfpga_flow/openfpga_cell_library/verilog/dff.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/openfpga_cell_library/verilog/gpio.v" `include "/home/tangxifan/test/OpenFPGA/openfpga_flow/openfpga_cell_library/verilog/gpio.v"
// ------ Include primitive module netlists ----- // ------ Include primitive module netlists -----
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/inv_buf_passgate.v" `include "sub_module/inv_buf_passgate.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/arch_encoder.v" `include "sub_module/arch_encoder.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/local_encoder.v" `include "sub_module/local_encoder.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/mux_primitives.v" `include "sub_module/mux_primitives.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/muxes.v" `include "sub_module/muxes.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/luts.v" `include "sub_module/luts.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/wires.v" `include "sub_module/wires.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/memories.v" `include "sub_module/memories.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/sub_module/shift_register_banks.v" `include "sub_module/shift_register_banks.v"
// ------ Include logic block netlists ----- // ------ Include logic block netlists -----
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_physical__iopad.v" `include "lb/logical_tile_io_mode_physical__iopad.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_io_.v" `include "lb/logical_tile_io_mode_io_.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.v" `include "lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff.v" `include "lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4.v" `include "lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle.v" `include "lb/logical_tile_clb_mode_default__fle.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_clb_.v" `include "lb/logical_tile_clb_mode_clb_.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/grid_io_top.v" `include "lb/grid_io_top.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/grid_io_right.v" `include "lb/grid_io_right.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/grid_io_bottom.v" `include "lb/grid_io_bottom.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/grid_io_left.v" `include "lb/grid_io_left.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/lb/grid_clb.v" `include "lb/grid_clb.v"
// ------ Include routing module netlists ----- // ------ Include routing module netlists -----
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/sb_0__0_.v" `include "routing/sb_0__0_.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/sb_0__1_.v" `include "routing/sb_0__1_.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/sb_1__0_.v" `include "routing/sb_1__0_.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/sb_1__1_.v" `include "routing/sb_1__1_.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/cbx_1__0_.v" `include "routing/cbx_1__0_.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/cbx_1__1_.v" `include "routing/cbx_1__1_.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/cby_0__1_.v" `include "routing/cby_0__1_.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/routing/cby_1__1_.v" `include "routing/cby_1__1_.v"
// ------ Include fabric top-level netlists ----- // ------ Include fabric top-level netlists -----
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fpga_top.v" `include "fpga_top.v"

6
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_include_netlists.v
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@ -8,9 +8,9 @@
`timescale 1ns / 1ps `timescale 1ns / 1ps
// ------ Include fabric top-level netlists ----- // ------ Include fabric top-level netlists -----
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_netlists.v" `include "fabric_netlists.v"
`include "and2_output_verilog.v" `include "and2_output_verilog.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_top_formal_verification.v" `include "and2_top_formal_verification.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v" `include "and2_formal_random_top_tb.v"

76
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_netlists.v
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@ -8,53 +8,53 @@
`timescale 1ns / 1ps `timescale 1ns / 1ps
// ------ Include defines: preproc flags ----- // ------ Include defines: preproc flags -----
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fpga_defines.v" `include "fpga_defines.v"
// ------ Include user-defined netlists ----- // ------ Include user-defined netlists -----
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/openfpga_cell_library/verilog/dff.v" `include "/home/tangxifan/test/OpenFPGA/openfpga_flow/openfpga_cell_library/verilog/dff.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/openfpga_cell_library/verilog/gpio.v" `include "/home/tangxifan/test/OpenFPGA/openfpga_flow/openfpga_cell_library/verilog/gpio.v"
// ------ Include primitive module netlists ----- // ------ Include primitive module netlists -----
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/inv_buf_passgate.v" `include "sub_module/inv_buf_passgate.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/arch_encoder.v" `include "sub_module/arch_encoder.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/local_encoder.v" `include "sub_module/local_encoder.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/mux_primitives.v" `include "sub_module/mux_primitives.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/muxes.v" `include "sub_module/muxes.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/luts.v" `include "sub_module/luts.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/wires.v" `include "sub_module/wires.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/memories.v" `include "sub_module/memories.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/sub_module/shift_register_banks.v" `include "sub_module/shift_register_banks.v"
// ------ Include logic block netlists ----- // ------ Include logic block netlists -----
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_physical__iopad.v" `include "lb/logical_tile_io_mode_physical__iopad.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_io_.v" `include "lb/logical_tile_io_mode_io_.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.v" `include "lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff.v" `include "lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4.v" `include "lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle.v" `include "lb/logical_tile_clb_mode_default__fle.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_clb_.v" `include "lb/logical_tile_clb_mode_clb_.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/grid_io_top.v" `include "lb/grid_io_top.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/grid_io_right.v" `include "lb/grid_io_right.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/grid_io_bottom.v" `include "lb/grid_io_bottom.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/grid_io_left.v" `include "lb/grid_io_left.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/lb/grid_clb.v" `include "lb/grid_clb.v"
// ------ Include routing module netlists ----- // ------ Include routing module netlists -----
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_0__0_.v" `include "routing/sb_0__0_.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_0__1_.v" `include "routing/sb_0__1_.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_0__4_.v" `include "routing/sb_0__4_.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_1__0_.v" `include "routing/sb_1__0_.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_1__1_.v" `include "routing/sb_1__1_.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_1__4_.v" `include "routing/sb_1__4_.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_4__0_.v" `include "routing/sb_4__0_.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_4__1_.v" `include "routing/sb_4__1_.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/sb_4__4_.v" `include "routing/sb_4__4_.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cbx_1__0_.v" `include "routing/cbx_1__0_.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cbx_1__1_.v" `include "routing/cbx_1__1_.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cbx_1__4_.v" `include "routing/cbx_1__4_.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cby_0__1_.v" `include "routing/cby_0__1_.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cby_1__1_.v" `include "routing/cby_1__1_.v"
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/routing/cby_4__1_.v" `include "routing/cby_4__1_.v"
// ------ Include fabric top-level netlists ----- // ------ Include fabric top-level netlists -----
`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fpga_top.v" `include "fpga_top.v"