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[Engine] Fixed a critical bug which causes undriven BL/WLs between shift register banks and child modules at the top-level module

This commit is contained in:
tangxifan 2021-10-01 17:38:26 -07:00
parent 977d81679d
commit 477c1cd062
3 changed files with 40 additions and 16 deletions
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11
openfpga/src/fabric/build_top_module_memory_bank.cpp
View File

@ -1188,7 +1188,6 @@ void add_top_module_nets_cmos_ql_memory_bank_shift_register_bank_blwls(ModuleMan
VTR_ASSERT(sr_module_blwl_port); VTR_ASSERT(sr_module_blwl_port);
BasicPort sr_module_blwl_port_info = module_manager.module_port(sr_bank_module, sr_module_blwl_port); BasicPort sr_module_blwl_port_info = module_manager.module_port(sr_bank_module, sr_module_blwl_port);
size_t cur_sr_module_blwl_pin_id = 0;
for (size_t sink_id = 0; sink_id < sr_banks.shift_register_bank_sink_child_ids(config_region, sr_bank_module, sr_bank_instance).size(); ++sink_id) { for (size_t sink_id = 0; sink_id < sr_banks.shift_register_bank_sink_child_ids(config_region, sr_bank_module, sr_bank_instance).size(); ++sink_id) {
size_t child_id = sr_banks.shift_register_bank_sink_child_ids(config_region, sr_bank_module, sr_bank_instance)[sink_id]; size_t child_id = sr_banks.shift_register_bank_sink_child_ids(config_region, sr_bank_module, sr_bank_instance)[sink_id];
@ -1199,7 +1198,7 @@ void add_top_module_nets_cmos_ql_memory_bank_shift_register_bank_blwls(ModuleMan
ModulePortId child_blwl_port = module_manager.find_module_port(child_module, child_blwl_port_name); ModulePortId child_blwl_port = module_manager.find_module_port(child_module, child_blwl_port_name);
BasicPort child_blwl_port_info = module_manager.module_port(child_module, child_blwl_port); BasicPort child_blwl_port_info = module_manager.module_port(child_module, child_blwl_port);
cur_sr_module_blwl_pin_id = cur_sr_module_blwl_pin_id % sr_module_blwl_port_info.get_width(); size_t cur_sr_module_blwl_pin_id = sr_banks.shift_register_bank_source_blwl_ids(config_region, sr_bank_module, sr_bank_instance)[sink_id];
/* Create net */ /* Create net */
ModuleNetId net = create_module_source_pin_net(module_manager, top_module, ModuleNetId net = create_module_source_pin_net(module_manager, top_module,
@ -1335,7 +1334,9 @@ void add_top_module_nets_cmos_ql_memory_bank_bl_shift_register_config_bus(Module
size_t bl_pin_id = bl_start_index_per_tile[coord.x()] + cur_bl_index; size_t bl_pin_id = bl_start_index_per_tile[coord.x()] + cur_bl_index;
sr_banks.add_shift_register_sink_nodes(config_region, sr_bank_module, cur_inst, child_id, sink_bl_pin); sr_banks.add_shift_register_sink_nodes(config_region, sr_bank_module, cur_inst, child_id, sink_bl_pin);
sr_banks.add_shift_register_sink_blwls(config_region, sr_bank_module, cur_inst, bl_pin_id); sr_banks.add_shift_register_source_blwls(config_region, sr_bank_module, cur_inst, bl_pin_id);
cur_bl_index++;
} }
} }
} }
@ -1426,7 +1427,9 @@ void add_top_module_nets_cmos_ql_memory_bank_wl_shift_register_config_bus(Module
for (const size_t& sink_wl_pin : child_wl_port_info.pins()) { for (const size_t& sink_wl_pin : child_wl_port_info.pins()) {
size_t wl_pin_id = wl_start_index_per_tile[coord.y()] + cur_wl_index; size_t wl_pin_id = wl_start_index_per_tile[coord.y()] + cur_wl_index;
sr_banks.add_shift_register_sink_nodes(config_region, sr_bank_module, cur_inst, child_id, sink_wl_pin); sr_banks.add_shift_register_sink_nodes(config_region, sr_bank_module, cur_inst, child_id, sink_wl_pin);
sr_banks.add_shift_register_sink_blwls(config_region, sr_bank_module, cur_inst, wl_pin_id); sr_banks.add_shift_register_source_blwls(config_region, sr_bank_module, cur_inst, wl_pin_id);
cur_wl_index++;
} }
} }
} }

21
openfpga/src/fabric/memory_bank_shift_register_banks.cpp
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@ -61,10 +61,23 @@ std::vector<size_t> MemoryBankShiftRegisterBanks::shift_register_bank_sink_pin_i
return std::vector<size_t>(); return std::vector<size_t>();
} }
std::vector<size_t> MemoryBankShiftRegisterBanks::shift_register_bank_source_blwl_ids(const ConfigRegionId& region,
const ModuleId& sr_module,
const size_t& sr_instance) const {
VTR_ASSERT(valid_region_id(region));
auto result = sr_instance_source_blwl_ids_[region].find(std::make_pair(sr_module, sr_instance));
/* Return an empty vector if not found */
if (result != sr_instance_source_blwl_ids_[region].end()) {
return result->second;
}
return std::vector<size_t>();
}
void MemoryBankShiftRegisterBanks::resize_regions(const size_t& num_regions) { void MemoryBankShiftRegisterBanks::resize_regions(const size_t& num_regions) {
sr_instance_sink_child_ids_.resize(num_regions); sr_instance_sink_child_ids_.resize(num_regions);
sr_instance_sink_child_pin_ids_.resize(num_regions); sr_instance_sink_child_pin_ids_.resize(num_regions);
sr_instance_sink_blwl_ids_.resize(num_regions); sr_instance_source_blwl_ids_.resize(num_regions);
} }
void MemoryBankShiftRegisterBanks::add_shift_register_instance(const ConfigRegionId& region, void MemoryBankShiftRegisterBanks::add_shift_register_instance(const ConfigRegionId& region,
@ -73,7 +86,7 @@ void MemoryBankShiftRegisterBanks::add_shift_register_instance(const ConfigRegio
VTR_ASSERT(valid_region_id(region)); VTR_ASSERT(valid_region_id(region));
sr_instance_sink_child_ids_[region][std::make_pair(sr_module, sr_instance)]; sr_instance_sink_child_ids_[region][std::make_pair(sr_module, sr_instance)];
sr_instance_sink_child_pin_ids_[region][std::make_pair(sr_module, sr_instance)]; sr_instance_sink_child_pin_ids_[region][std::make_pair(sr_module, sr_instance)];
sr_instance_sink_blwl_ids_[region][std::make_pair(sr_module, sr_instance)]; sr_instance_source_blwl_ids_[region][std::make_pair(sr_module, sr_instance)];
} }
void MemoryBankShiftRegisterBanks::add_shift_register_sink_nodes(const ConfigRegionId& region, void MemoryBankShiftRegisterBanks::add_shift_register_sink_nodes(const ConfigRegionId& region,
@ -86,12 +99,12 @@ void MemoryBankShiftRegisterBanks::add_shift_register_sink_nodes(const ConfigReg
sr_instance_sink_child_pin_ids_[region][std::make_pair(sr_module, sr_instance)].push_back(sink_child_pin_id); sr_instance_sink_child_pin_ids_[region][std::make_pair(sr_module, sr_instance)].push_back(sink_child_pin_id);
} }
void MemoryBankShiftRegisterBanks::add_shift_register_sink_blwls(const ConfigRegionId& region, void MemoryBankShiftRegisterBanks::add_shift_register_source_blwls(const ConfigRegionId& region,
const ModuleId& sr_module, const ModuleId& sr_module,
const size_t& sr_instance, const size_t& sr_instance,
const size_t& sink_blwl_id) { const size_t& sink_blwl_id) {
VTR_ASSERT(valid_region_id(region)); VTR_ASSERT(valid_region_id(region));
sr_instance_sink_blwl_ids_[region][std::make_pair(sr_module, sr_instance)].push_back(sink_blwl_id); sr_instance_source_blwl_ids_[region][std::make_pair(sr_module, sr_instance)].push_back(sink_blwl_id);
} }
bool MemoryBankShiftRegisterBanks::valid_region_id(const ConfigRegionId& region) const { bool MemoryBankShiftRegisterBanks::valid_region_id(const ConfigRegionId& region) const {

12
openfpga/src/fabric/memory_bank_shift_register_banks.h
View File

@ -44,6 +44,14 @@ class MemoryBankShiftRegisterBanks {
std::vector<size_t> shift_register_bank_sink_pin_ids(const ConfigRegionId& region, std::vector<size_t> shift_register_bank_sink_pin_ids(const ConfigRegionId& region,
const ModuleId& sr_module, const ModuleId& sr_module,
const size_t& sr_instance) const; const size_t& sr_instance) const;
/* @brief Return a list of BL/WL ids of a given instance of shift register bank
* under a specific configuration region of top-level module
*/
std::vector<size_t> shift_register_bank_source_blwl_ids(const ConfigRegionId& region,
const ModuleId& sr_module,
const size_t& sr_instance) const;
public: /* Mutators */ public: /* Mutators */
void resize_regions(const size_t& num_regions); void resize_regions(const size_t& num_regions);
@ -60,7 +68,7 @@ class MemoryBankShiftRegisterBanks {
const size_t& sink_child_pin_id); const size_t& sink_child_pin_id);
/* @brief Add the BL/WL id under a specific configuration region of top-level module to which a shift register is connected to */ /* @brief Add the BL/WL id under a specific configuration region of top-level module to which a shift register is connected to */
void add_shift_register_sink_blwls(const ConfigRegionId& region, void add_shift_register_source_blwls(const ConfigRegionId& region,
const ModuleId& sr_module, const ModuleId& sr_module,
const size_t& sr_instance, const size_t& sr_instance,
const size_t& sink_blwl_id); const size_t& sink_blwl_id);
@ -71,7 +79,7 @@ class MemoryBankShiftRegisterBanks {
/* [config_region][(shift_register_module, shift_register_instance)][i] = (reconfigurable_child_id, blwl_port_pin_index)*/ /* [config_region][(shift_register_module, shift_register_instance)][i] = (reconfigurable_child_id, blwl_port_pin_index)*/
vtr::vector<ConfigRegionId, std::map<std::pair<ModuleId, size_t>, std::vector<size_t>>> sr_instance_sink_child_ids_; vtr::vector<ConfigRegionId, std::map<std::pair<ModuleId, size_t>, std::vector<size_t>>> sr_instance_sink_child_ids_;
vtr::vector<ConfigRegionId, std::map<std::pair<ModuleId, size_t>, std::vector<size_t>>> sr_instance_sink_child_pin_ids_; vtr::vector<ConfigRegionId, std::map<std::pair<ModuleId, size_t>, std::vector<size_t>>> sr_instance_sink_child_pin_ids_;
vtr::vector<ConfigRegionId, std::map<std::pair<ModuleId, size_t>, std::vector<size_t>>> sr_instance_sink_blwl_ids_; vtr::vector<ConfigRegionId, std::map<std::pair<ModuleId, size_t>, std::vector<size_t>>> sr_instance_source_blwl_ids_;
}; };
} /* end namespace openfpga */ } /* end namespace openfpga */