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[HDL] Rename tech lib to be consistent with arch name changes

This commit is contained in:
tangxifan 2021-03-20 18:08:03 -06:00
parent 911979a731
commit 477a522885
4 changed files with 30 additions and 0 deletions
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0
openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_40nm_bram.txt → openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram.txt
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0
openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_40nm_bram_map.v → openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram_map.v
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13
openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_40nm_cell_sim.v → openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_cell_sim.v
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@ -57,3 +57,16 @@ module dpram_1024x8 (
endmodule
//-----------------------------
// 36-bit multiplier
//-----------------------------
module mult_36(
input [35:0] A,
input [35:0] B,
output [71:0] Y
);
assign Y = A * B;
endmodule

17
openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_dsp_map.v Normal file
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@ -0,0 +1,17 @@
module mult_36x36 (
input [35:0] A,
input [35:0] B,
output [71:0] Y
);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
mult_36 #() _TECHMAP_REPLACE_ (
.A (A),
.B (B),
.Y (Y) );
endmodule