From 46fa1197b0fcb7c2e50a63d4b4eb4c4960d5e1ae Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Wed, 29 May 2019 16:43:56 -0600 Subject: [PATCH] Test reading tech file --- vpr7_x2p/vpr/.regression_verilog.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr7_x2p/vpr/.regression_verilog.sh b/vpr7_x2p/vpr/.regression_verilog.sh index fa49c48a9..c617f6b4b 100755 --- a/vpr7_x2p/vpr/.regression_verilog.sh +++ b/vpr7_x2p/vpr/.regression_verilog.sh @@ -37,7 +37,7 @@ rm -rf $verilog_output_dirpath/$verilog_output_dirname # Run VPR #valgrind -./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_modelsim_autodeck $modelsim_ini_file --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_sdc_pnr --fpga_verilog_print_report_timing_tcl #--fpga_verilog_print_sdc_analysis +./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_modelsim_autodeck $modelsim_ini_file --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_sdc_pnr --fpga_verilog_print_report_timing_tcl --power --tech_properties ../../fpga_flow/tech/PTM_45nm/45nm.xml #--fpga_verilog_print_sdc_analysis