From 462886fb5fd6e3a1b3734224a8afa091ee7675e6 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 29 Sep 2020 14:02:03 -0600
Subject: [PATCH] [Documentation] Update documentation for the multiple region
 support on configuration chain

---
 docs/source/manual/arch_lang/config_protocol.rst | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/docs/source/manual/arch_lang/config_protocol.rst b/docs/source/manual/arch_lang/config_protocol.rst
index 48fd66ac3..6c76c5663 100644
--- a/docs/source/manual/arch_lang/config_protocol.rst
+++ b/docs/source/manual/arch_lang/config_protocol.rst
@@ -49,7 +49,7 @@ It will use the circuit model defined in :numref:`fig_ccff`.
 .. code-block:: xml
 
   <configuration_protocol>
-    <organization type="scan_chain" circuit_model_name="ccff"/>
+    <organization type="scan_chain" circuit_model_name="ccff" num_regions="<int>"/>
   </configuration_protocol>
 
 .. _fig_ccff_fpga:
@@ -60,6 +60,10 @@ It will use the circuit model defined in :numref:`fig_ccff`.
  
    Example of a configuration chain to program core logic of a FPGA 
 
+.. option:: num_regions="<int>"
+
+  Specify the number of configuration chains to be used across the fabrics. By default, it will be only 1 configuration chain. The more configuration chain to be used, the fast configuration runtime will be, but at the cost of more I/Os in the FPGA fabrics.
+
 Frame-based Example
 ~~~~~~~~~~~~~~~~~~~
 The following XML code describes frame-based memory banks to configure the core logic of FPGA.