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[FPGA-Verilog] Rename files and functions to distinguish from FPGA-SPICE files and functions

This commit is contained in:
tangxifan 2020-09-20 12:58:55 -06:00
parent 222bc86cbf
commit 460fef5807
6 changed files with 28 additions and 28 deletions
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14
openfpga/src/fpga_verilog/verilog_api.cpp
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@ -24,7 +24,7 @@
#include "verilog_preconfig_top_module.h" #include "verilog_preconfig_top_module.h"
#include "verilog_formal_random_top_testbench.h" #include "verilog_formal_random_top_testbench.h"
#include "verilog_top_testbench.h" #include "verilog_top_testbench.h"
#include "simulation_info_writer.h" #include "verilog_simulation_info_writer.h"
/* Header file for this source file */ /* Header file for this source file */
#include "verilog_api.h" #include "verilog_api.h"
@ -128,9 +128,9 @@ void fpga_fabric_verilog(ModuleManager &module_manager,
options.explicit_port_mapping()); options.explicit_port_mapping());
/* Generate an netlist including all the fabric-related netlists */ /* Generate an netlist including all the fabric-related netlists */
print_fabric_include_netlist(const_cast<const NetlistManager &>(netlist_manager), print_verilog_fabric_include_netlist(const_cast<const NetlistManager &>(netlist_manager),
src_dir_path, src_dir_path,
circuit_lib); circuit_lib);
/* Given a brief stats on how many Verilog modules have been written to files */ /* Given a brief stats on how many Verilog modules have been written to files */
VTR_LOGV(options.verbose_output(), VTR_LOGV(options.verbose_output(),
@ -233,9 +233,9 @@ void fpga_verilog_testbench(const ModuleManager &module_manager,
} }
/* Generate a Verilog file including all the netlists that have been generated */ /* Generate a Verilog file including all the netlists that have been generated */
print_include_netlists(src_dir_path, print_verilog_testbench_include_netlists(src_dir_path,
netlist_name, netlist_name,
options.reference_benchmark_file_path()); options.reference_benchmark_file_path());
} }
} /* end namespace openfpga */ } /* end namespace openfpga */

18
openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
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@ -30,10 +30,10 @@ namespace openfpga {
* This does NOT include any testbenches! * This does NOT include any testbenches!
* Some netlists are open to compile under specific preprocessing flags * Some netlists are open to compile under specific preprocessing flags
*******************************************************************/ *******************************************************************/
void print_fabric_include_netlist(const NetlistManager& netlist_manager, void print_verilog_fabric_include_netlist(const NetlistManager& netlist_manager,
const std::string& src_dir, const std::string& src_dir,
const CircuitLibrary& circuit_lib) { const CircuitLibrary& circuit_lib) {
std::string verilog_fname = src_dir + std::string(FABRIC_INCLUDE_NETLIST_FILE_NAME); std::string verilog_fname = src_dir + std::string(FABRIC_INCLUDE_VERILOG_NETLIST_FILE_NAME);
/* Create the file stream */ /* Create the file stream */
std::fstream fp; std::fstream fp;
@ -94,10 +94,10 @@ void print_fabric_include_netlist(const NetlistManager& netlist_manager,
* that have been generated and user-defined. * that have been generated and user-defined.
* Some netlists are open to compile under specific preprocessing flags * Some netlists are open to compile under specific preprocessing flags
*******************************************************************/ *******************************************************************/
void print_include_netlists(const std::string& src_dir, void print_verilog_testbench_include_netlists(const std::string& src_dir,
const std::string& circuit_name, const std::string& circuit_name,
const std::string& reference_benchmark_file) { const std::string& reference_benchmark_file) {
std::string verilog_fname = src_dir + circuit_name + std::string(TOP_INCLUDE_NETLIST_FILE_NAME_POSTFIX); std::string verilog_fname = src_dir + circuit_name + std::string(TOP_VERILOG_TESTBENCH_INCLUDE_NETLIST_FILE_NAME_POSTFIX);
/* Create the file stream */ /* Create the file stream */
std::fstream fp; std::fstream fp;
@ -116,7 +116,7 @@ void print_include_netlists(const std::string& src_dir,
/* Include FPGA top module */ /* Include FPGA top module */
print_verilog_comment(fp, std::string("------ Include fabric top-level netlists -----")); print_verilog_comment(fp, std::string("------ Include fabric top-level netlists -----"));
print_verilog_include_netlist(fp, src_dir + std::string(FABRIC_INCLUDE_NETLIST_FILE_NAME)); print_verilog_include_netlist(fp, src_dir + std::string(FABRIC_INCLUDE_VERILOG_NETLIST_FILE_NAME));
fp << std::endl; fp << std::endl;
/* Include reference benchmark netlist only when auto-check flag is enabled */ /* Include reference benchmark netlist only when auto-check flag is enabled */

12
openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h
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@ -17,13 +17,13 @@
/* begin namespace openfpga */ /* begin namespace openfpga */
namespace openfpga { namespace openfpga {
void print_fabric_include_netlist(const NetlistManager& netlist_manager, void print_verilog_fabric_include_netlist(const NetlistManager& netlist_manager,
const std::string& src_dir, const std::string& src_dir,
const CircuitLibrary& circuit_lib); const CircuitLibrary& circuit_lib);
void print_include_netlists(const std::string& src_dir, void print_verilog_testbench_include_netlists(const std::string& src_dir,
const std::string& circuit_name, const std::string& circuit_name,
const std::string& reference_benchmark_file); const std::string& reference_benchmark_file);
void print_verilog_preprocessing_flags_netlist(const std::string& src_dir, void print_verilog_preprocessing_flags_netlist(const std::string& src_dir,
const FabricVerilogOption& fabric_verilog_opts); const FabricVerilogOption& fabric_verilog_opts);

4
openfpga/src/fpga_verilog/verilog_constants.h
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@ -19,8 +19,8 @@ constexpr char* MODELSIM_SIMULATION_TIME_UNIT = "ms";
constexpr char* ICARUS_SIMULATOR_FLAG = "ICARUS_SIMULATOR"; // the flag to enable specific Verilog code in testbenches constexpr char* ICARUS_SIMULATOR_FLAG = "ICARUS_SIMULATOR"; // the flag to enable specific Verilog code in testbenches
// End of Icarus variables and flag // End of Icarus variables and flag
constexpr char* FABRIC_INCLUDE_NETLIST_FILE_NAME = "fabric_netlists.v"; constexpr char* FABRIC_INCLUDE_VERILOG_NETLIST_FILE_NAME = "fabric_netlists.v";
constexpr char* TOP_INCLUDE_NETLIST_FILE_NAME_POSTFIX = "_include_netlists.v"; constexpr char* TOP_VERILOG_TESTBENCH_INCLUDE_NETLIST_FILE_NAME_POSTFIX = "_include_netlists.v";
constexpr char* VERILOG_TOP_POSTFIX = "_top.v"; constexpr char* VERILOG_TOP_POSTFIX = "_top.v";
constexpr char* FORMAL_VERIFICATION_VERILOG_FILE_POSTFIX = "_top_formal_verification.v"; constexpr char* FORMAL_VERIFICATION_VERILOG_FILE_POSTFIX = "_top_formal_verification.v";
constexpr char* TOP_TESTBENCH_VERILOG_FILE_POSTFIX = "_top_tb.v"; /* !!! must be consist with the modelsim_testbench_module_postfix */ constexpr char* TOP_TESTBENCH_VERILOG_FILE_POSTFIX = "_top_tb.v"; /* !!! must be consist with the modelsim_testbench_module_postfix */

4
openfpga/src/fpga_verilog/simulation_info_writer.cpp → openfpga/src/fpga_verilog/verilog_simulation_info_writer.cpp
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@ -21,7 +21,7 @@
#include "simulation_utils.h" #include "simulation_utils.h"
#include "verilog_constants.h" #include "verilog_constants.h"
#include "simulation_info_writer.h" #include "verilog_simulation_info_writer.h"
/* begin namespace openfpga */ /* begin namespace openfpga */
namespace openfpga { namespace openfpga {
@ -77,7 +77,7 @@ void print_verilog_simulation_info(const std::string& ini_fname,
ini["SIMULATION_DECK"]["UNIT "] = "ms"; ini["SIMULATION_DECK"]["UNIT "] = "ms";
ini["SIMULATION_DECK"]["VERILOG_PATH "] = std::string(src_dir); ini["SIMULATION_DECK"]["VERILOG_PATH "] = std::string(src_dir);
ini["SIMULATION_DECK"]["VERILOG_FILE1"] = std::string(DEFINES_VERILOG_FILE_NAME); ini["SIMULATION_DECK"]["VERILOG_FILE1"] = std::string(DEFINES_VERILOG_FILE_NAME);
ini["SIMULATION_DECK"]["VERILOG_FILE2"] = std::string(circuit_name + std::string(TOP_INCLUDE_NETLIST_FILE_NAME_POSTFIX)); ini["SIMULATION_DECK"]["VERILOG_FILE2"] = std::string(circuit_name + std::string(TOP_VERILOG_TESTBENCH_INCLUDE_NETLIST_FILE_NAME_POSTFIX));
ini["SIMULATION_DECK"]["CONFIG_PROTOCOL"] = std::string(CONFIG_PROTOCOL_TYPE_STRING[config_protocol_type]); ini["SIMULATION_DECK"]["CONFIG_PROTOCOL"] = std::string(CONFIG_PROTOCOL_TYPE_STRING[config_protocol_type]);
/* Information required by UVM */ /* Information required by UVM */

4
openfpga/src/fpga_verilog/simulation_info_writer.h → openfpga/src/fpga_verilog/verilog_simulation_info_writer.h
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@ -1,5 +1,5 @@
#ifndef SIMULATION_INFO_WRITER_H #ifndef VERILOG_SIMULATION_INFO_WRITER_H
#define SIMULATION_INFO_WRITER_H #define VERILOG_SIMULATION_INFO_WRITER_H
/******************************************************************** /********************************************************************
* Include header files that are required by function declaration * Include header files that are required by function declaration