diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga_synthesizable.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga_synthesizable.xml
index 50c2769ad..95ccc9e2d 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga_synthesizable.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga_synthesizable.xml
@@ -52,7 +52,7 @@
         10e-12
       </delay_matrix>
     </circuit_model>
-    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/tap_buf4.v>
       <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
       <device_technology device_model_name="logic"/>
       <port type="input" prefix="in" size="1"/>
@@ -131,7 +131,7 @@
       <port type="sram" prefix="sram" size="1"/>
     </circuit_model>
     <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dffsrq.v">
+    <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
@@ -156,7 +156,7 @@
       <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="DFFR" default_val="1"/>
     </circuit_model>
     <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dffr.v">
+    <circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
diff --git a/openfpga_flow/openfpga_cell_library/verilog/dffr.v b/openfpga_flow/openfpga_cell_library/verilog/dffr.v
deleted file mode 100644
index 051fa71fb..000000000
--- a/openfpga_flow/openfpga_cell_library/verilog/dffr.v
+++ /dev/null
@@ -1,35 +0,0 @@
-module DFFR(RST,
-            CK,
-            D,
-            Q,
-						QN);
-//----- GLOBAL PORTS -----
-input [0:0] RST;
-//----- GLOBAL PORTS -----
-input [0:0] CK;
-//----- INPUT PORTS -----
-input [0:0] D;
-//----- OUTPUT PORTS -----
-output reg [0:0] Q;
-output reg [0:0] QN;
-
-//----- BEGIN wire-connection ports -----
-//----- END wire-connection ports -----
-
-
-//----- BEGIN Registered ports -----
-//----- END Registered ports -----
-
-// ----- Internal logic should start here -----
-always @(posedge CK) begin
-  if(RST) begin
-    Q <= 1'b0;
-    QN <= 1'b1;
-  end else begin
-    Q <= D;
-    QN <= ~D;
-  end
-end
-
-// ----- Internal logic should end here -----
-endmodule
diff --git a/openfpga_flow/openfpga_cell_library/verilog/dffsrq.v b/openfpga_flow/openfpga_cell_library/verilog/dffsrq.v
deleted file mode 100644
index cff8848a9..000000000
--- a/openfpga_flow/openfpga_cell_library/verilog/dffsrq.v
+++ /dev/null
@@ -1,36 +0,0 @@
-module DFFSRQ(SET,
-            RST,
-            CK,
-            D,
-            Q);
-//----- GLOBAL PORTS -----
-input [0:0] SET;
-//----- GLOBAL PORTS -----
-input [0:0] RST;
-//----- GLOBAL PORTS -----
-input [0:0] CK;
-//----- INPUT PORTS -----
-input [0:0] D;
-//----- OUTPUT PORTS -----
-output reg [0:0] Q;
-
-//----- BEGIN wire-connection ports -----
-//----- END wire-connection ports -----
-
-
-//----- BEGIN Registered ports -----
-//----- END Registered ports -----
-
-// ----- Internal logic should start here -----
-always @(posedge CK) begin
-  if(RST) begin
-    Q <= 1'b0;
-  end else if(SET) begin
-    Q <= 1'b1;
-  end else begin
-    Q <= D;
-  end
-end
-
-// ----- Internal logic should end here -----
-endmodule
diff --git a/openfpga_flow/openfpga_cell_library/verilog/tap_buf4.v b/openfpga_flow/openfpga_cell_library/verilog/tap_buf4.v
new file mode 100644
index 000000000..cb0be94c5
--- /dev/null
+++ b/openfpga_flow/openfpga_cell_library/verilog/tap_buf4.v
@@ -0,0 +1,28 @@
+// ----- Verilog module for tap_buf4 -----
+module tap_buf4(in,
+                out);
+//----- INPUT PORTS -----
+input [0:0] in;
+//----- OUTPUT PORTS -----
+output [0:0] out;
+
+//----- BEGIN wire-connection ports -----
+//----- END wire-connection ports -----
+
+
+//----- BEGIN Registered ports -----
+//----- END Registered ports -----
+
+// ----- Verilog codes of a regular inverter -----
+  //assign out = (in === 1'bz)? $random : ~in;
+  assign out = ~in;
+
+`ifdef ENABLE_TIMING
+// ------ BEGIN Pin-to-pin Timing constraints -----
+  specify
+    (in[0] => out[0]) = (0.01, 0.01);
+  endspecify
+// ------ END Pin-to-pin Timing constraints -----
+`endif
+endmodule
+// ----- END Verilog module for tap_buf4 -----