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[Tool] Support multiple memory banks in top-level module

This commit is contained in:
tangxifan 2020-10-29 12:42:03 -06:00
parent bd49ea95d4
commit 448e88645a
7 changed files with 400 additions and 241 deletions
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8
openfpga/src/fabric/build_top_module.cpp
View File

@ -437,13 +437,13 @@ int build_top_module(ModuleManager& module_manager,
* This is a much easier job after adding sub modules (instances),
* we just need to find all the I/O ports from the child modules and build a list of it
*/
size_t module_num_config_bits = find_module_num_config_bits_from_child_modules(module_manager, top_module, circuit_lib, sram_model, config_protocol.type());
vtr::vector<ConfigRegionId, size_t> top_module_num_config_bits = find_top_module_regional_num_config_bit(module_manager, top_module, circuit_lib, sram_model, config_protocol.type());
if (0 < module_num_config_bits) {
if (!top_module_num_config_bits.empty()) {
add_top_module_sram_ports(module_manager, top_module,
circuit_lib, sram_model,
config_protocol, module_num_config_bits);
config_protocol,
top_module_num_config_bits);
}
/* Add module nets to connect memory cells inside
@ -453,7 +453,7 @@ int build_top_module(ModuleManager& module_manager,
add_top_module_nets_memory_config_bus(module_manager, decoder_lib,
top_module,
config_protocol, circuit_lib.design_tech_type(sram_model),
module_num_config_bits);
top_module_num_config_bits);
}
return status;

183
openfpga/src/fabric/build_top_module_memory.cpp
View File

@ -616,7 +616,7 @@ vtr::vector<ConfigRegionId, size_t> find_top_module_regional_num_config_bit(cons
*/
for (const ConfigRegionId& config_region : module_manager.regions(top_module)) {
for (const ModuleId& child_module : module_manager.region_configurable_children(top_module, config_region)) {
num_config_bits[config_region] = find_module_num_config_bits(module_manager, child_module, circuit_lib, sram_model, config_protocol_type);
num_config_bits[config_region] += find_module_num_config_bits(module_manager, child_module, circuit_lib, sram_model, config_protocol_type);
}
}
break;
@ -671,10 +671,9 @@ size_t generate_top_module_sram_port_size(const ConfigProtocol& config_protocol,
case CONFIG_MEM_STANDALONE:
break;
case CONFIG_MEM_SCAN_CHAIN:
/* CCFF head/tail are single-bit ports */
sram_port_size = config_protocol.num_regions();
break;
case CONFIG_MEM_MEMORY_BANK:
/* CCFF head/tail, data input could be multi-bit ports */
sram_port_size = config_protocol.num_regions();
break;
case CONFIG_MEM_FRAME_BASED:
break;
@ -715,9 +714,13 @@ void add_top_module_sram_ports(ModuleManager& module_manager,
const CircuitLibrary& circuit_lib,
const CircuitModelId& sram_model,
const ConfigProtocol& config_protocol,
const size_t& num_config_bits) {
const vtr::vector<ConfigRegionId, size_t>& num_config_bits) {
std::vector<std::string> sram_port_names = generate_sram_port_names(circuit_lib, sram_model, config_protocol.type());
size_t sram_port_size = generate_top_module_sram_port_size(config_protocol, num_config_bits);
size_t total_num_config_bits = 0;
for (const size_t& curr_num_config_bits : num_config_bits) {
total_num_config_bits += curr_num_config_bits;
}
size_t sram_port_size = generate_top_module_sram_port_size(config_protocol, total_num_config_bits);
/* Add ports to the module manager */
switch (config_protocol.type()) {
@ -733,15 +736,24 @@ void add_top_module_sram_ports(ModuleManager& module_manager,
BasicPort en_port(std::string(DECODER_ENABLE_PORT_NAME), 1);
module_manager.add_port(module_id, en_port, ModuleManager::MODULE_INPUT_PORT);
size_t bl_addr_size = find_memory_decoder_addr_size(num_config_bits);
/* BL address size is the largest among all the regions */
size_t bl_addr_size = 0;
for (const ConfigRegionId& config_region : module_manager.regions(module_id)) {
bl_addr_size = std::max(bl_addr_size, find_memory_decoder_addr_size(num_config_bits[config_region]));
}
BasicPort bl_addr_port(std::string(DECODER_BL_ADDRESS_PORT_NAME), bl_addr_size);
module_manager.add_port(module_id, bl_addr_port, ModuleManager::MODULE_INPUT_PORT);
size_t wl_addr_size = find_memory_decoder_addr_size(num_config_bits);
/* WL address size is the largest among all the regions */
size_t wl_addr_size = 0;
for (const ConfigRegionId& config_region : module_manager.regions(module_id)) {
wl_addr_size = std::max(wl_addr_size, find_memory_decoder_addr_size(num_config_bits[config_region]));
}
BasicPort wl_addr_port(std::string(DECODER_WL_ADDRESS_PORT_NAME), wl_addr_size);
module_manager.add_port(module_id, wl_addr_port, ModuleManager::MODULE_INPUT_PORT);
BasicPort din_port(std::string(DECODER_DATA_IN_PORT_NAME), 1);
/* Data input should be dependent on the number of configuration regions*/
BasicPort din_port(std::string(DECODER_DATA_IN_PORT_NAME), config_protocol.num_regions());
module_manager.add_port(module_id, din_port, ModuleManager::MODULE_INPUT_PORT);
break;
@ -770,7 +782,7 @@ void add_top_module_sram_ports(ModuleManager& module_manager,
BasicPort en_port(std::string(DECODER_ENABLE_PORT_NAME), 1);
module_manager.add_port(module_id, en_port, ModuleManager::MODULE_INPUT_PORT);
BasicPort addr_port(std::string(DECODER_ADDRESS_PORT_NAME), num_config_bits);
BasicPort addr_port(std::string(DECODER_ADDRESS_PORT_NAME), total_num_config_bits);
module_manager.add_port(module_id, addr_port, ModuleManager::MODULE_INPUT_PORT);
BasicPort din_port(std::string(DECODER_DATA_IN_PORT_NAME), 1);
@ -787,11 +799,29 @@ void add_top_module_sram_ports(ModuleManager& module_manager,
/*********************************************************************
* Top-level function to add nets for memory banks
* - Find the number of BLs and WLs required
* Each configuration region has independent memory bank circuitry
* - Find the number of BLs and WLs required for each region
* - Create BL and WL decoders, and add them to decoder library
* - Create nets to connect from top-level module inputs to inputs of decoders
* - Create nets to connect from outputs of decoders to BL/WL of configurable children
*
* Detailed schematic of how memory banks are connected in the top-level:
* Consider a random Region X, local BL address lines are aligned to the LSB of the
* top-level BL address lines
*
* top_bl_addr[N-1:0]
* ^
* | local_bl_addr[M-1:0], N > M
* |
* +-----+------------------+
* | | |
* | +-------------------+ |
* | | Word Line Decoder | |
* | +-------------------+ |
* | |
*
* Detailed schematic of each memory bank:
*
* WL_enable WL address
* | |
* v v
@ -834,7 +864,7 @@ static
void add_top_module_nets_cmos_memory_bank_config_bus(ModuleManager& module_manager,
DecoderLibrary& decoder_lib,
const ModuleId& top_module,
const size_t& num_config_bits) {
const vtr::vector<ConfigRegionId, size_t>& num_config_bits) {
/* Find Enable port from the top-level module */
ModulePortId en_port = module_manager.find_module_port(top_module, std::string(DECODER_ENABLE_PORT_NAME));
BasicPort en_port_info = module_manager.module_port(top_module, en_port);
@ -843,6 +873,9 @@ void add_top_module_nets_cmos_memory_bank_config_bus(ModuleManager& module_manag
ModulePortId din_port = module_manager.find_module_port(top_module, std::string(DECODER_DATA_IN_PORT_NAME));
BasicPort din_port_info = module_manager.module_port(top_module, din_port);
/* Data in port should match the number of configuration regions */
VTR_ASSERT(din_port_info.get_width() == module_manager.regions(top_module).size());
/* Find BL and WL address port from the top-level module */
ModulePortId bl_addr_port = module_manager.find_module_port(top_module, std::string(DECODER_BL_ADDRESS_PORT_NAME));
BasicPort bl_addr_port_info = module_manager.module_port(top_module, bl_addr_port);
@ -850,26 +883,36 @@ void add_top_module_nets_cmos_memory_bank_config_bus(ModuleManager& module_manag
ModulePortId wl_addr_port = module_manager.find_module_port(top_module, std::string(DECODER_WL_ADDRESS_PORT_NAME));
BasicPort wl_addr_port_info = module_manager.module_port(top_module, wl_addr_port);
/* Find the number of BLs and WLs required to access each memory bit */
size_t bl_addr_size = bl_addr_port_info.get_width();
size_t wl_addr_size = wl_addr_port_info.get_width();
size_t num_bls = find_memory_decoder_data_size(num_config_bits);
size_t num_wls = find_memory_decoder_data_size(num_config_bits);
/* Find the top-level number of BLs and WLs required to access each memory bit */
size_t top_bl_addr_size = bl_addr_port_info.get_width();
size_t top_wl_addr_size = wl_addr_port_info.get_width();
/* Add the BL decoder module
/* Create separated memory bank circuitry, i.e., BL/WL decoders for each region */
for (const ConfigRegionId& config_region : module_manager.regions(top_module)) {
/* Find the number of BL/WLs and address sizes for the local decoders in the region */
size_t num_bls = find_memory_decoder_data_size(num_config_bits[config_region]);
size_t num_wls = find_memory_decoder_data_size(num_config_bits[config_region]);
size_t local_bl_addr_size = find_memory_decoder_addr_size(num_config_bits[config_region]);
size_t local_wl_addr_size = find_memory_decoder_addr_size(num_config_bits[config_region]);
VTR_ASSERT(top_bl_addr_size >= local_bl_addr_size);
VTR_ASSERT(top_wl_addr_size >= local_wl_addr_size);
/**************************************************************
* Add the BL decoder module
* Search the decoder library
* If we find one, we use the module.
* Otherwise, we create one and add it to the decoder library
*/
DecoderId bl_decoder_id = decoder_lib.find_decoder(bl_addr_size, num_bls,
DecoderId bl_decoder_id = decoder_lib.find_decoder(local_bl_addr_size, num_bls,
true, true, false);
if (DecoderId::INVALID() == bl_decoder_id) {
bl_decoder_id = decoder_lib.add_decoder(bl_addr_size, num_bls, true, true, false);
bl_decoder_id = decoder_lib.add_decoder(local_bl_addr_size, num_bls, true, true, false);
}
VTR_ASSERT(DecoderId::INVALID() != bl_decoder_id);
/* Create a module if not existed yet */
std::string bl_decoder_module_name = generate_memory_decoder_with_data_in_subckt_name(bl_addr_size, num_bls);
std::string bl_decoder_module_name = generate_memory_decoder_with_data_in_subckt_name(local_bl_addr_size, num_bls);
ModuleId bl_decoder_module = module_manager.find_module(bl_decoder_module_name);
if (ModuleId::INVALID() == bl_decoder_module) {
/* BL decoder has the same ports as the frame-based decoders
@ -880,23 +923,24 @@ void add_top_module_nets_cmos_memory_bank_config_bus(ModuleManager& module_manag
bl_decoder_id);
}
VTR_ASSERT(ModuleId::INVALID() != bl_decoder_module);
VTR_ASSERT(0 == module_manager.num_instance(top_module, bl_decoder_module));
size_t curr_bl_decoder_instance_id = module_manager.num_instance(top_module, bl_decoder_module);
module_manager.add_child_module(top_module, bl_decoder_module);
/* Add the WL decoder module
/**************************************************************
* Add the WL decoder module
* Search the decoder library
* If we find one, we use the module.
* Otherwise, we create one and add it to the decoder library
*/
DecoderId wl_decoder_id = decoder_lib.find_decoder(wl_addr_size, num_wls,
DecoderId wl_decoder_id = decoder_lib.find_decoder(local_wl_addr_size, num_wls,
true, false, false);
if (DecoderId::INVALID() == wl_decoder_id) {
wl_decoder_id = decoder_lib.add_decoder(wl_addr_size, num_wls, true, false, false);
wl_decoder_id = decoder_lib.add_decoder(local_wl_addr_size, num_wls, true, false, false);
}
VTR_ASSERT(DecoderId::INVALID() != wl_decoder_id);
/* Create a module if not existed yet */
std::string wl_decoder_module_name = generate_memory_decoder_subckt_name(wl_addr_size, num_wls);
std::string wl_decoder_module_name = generate_memory_decoder_subckt_name(local_wl_addr_size, num_wls);
ModuleId wl_decoder_module = module_manager.find_module(wl_decoder_module_name);
if (ModuleId::INVALID() == wl_decoder_module) {
/* BL decoder has the same ports as the frame-based decoders
@ -907,10 +951,12 @@ void add_top_module_nets_cmos_memory_bank_config_bus(ModuleManager& module_manag
wl_decoder_id);
}
VTR_ASSERT(ModuleId::INVALID() != wl_decoder_module);
VTR_ASSERT(0 == module_manager.num_instance(top_module, wl_decoder_module));
size_t curr_wl_decoder_instance_id = module_manager.num_instance(top_module, wl_decoder_module);
module_manager.add_child_module(top_module, wl_decoder_module);
/* Add module nets from the top module to BL decoder's inputs */
/**************************************************************
* Add module nets from the top module to BL decoder's inputs
*/
ModulePortId bl_decoder_en_port = module_manager.find_module_port(bl_decoder_module, std::string(DECODER_ENABLE_PORT_NAME));
BasicPort bl_decoder_en_port_info = module_manager.module_port(bl_decoder_module, bl_decoder_en_port);
@ -920,25 +966,42 @@ void add_top_module_nets_cmos_memory_bank_config_bus(ModuleManager& module_manag
ModulePortId bl_decoder_din_port = module_manager.find_module_port(bl_decoder_module, std::string(DECODER_DATA_IN_PORT_NAME));
BasicPort bl_decoder_din_port_info = module_manager.module_port(bl_decoder_module, bl_decoder_din_port);
/* Data in port of the local BL decoder should always be 1 */
VTR_ASSERT(1 == bl_decoder_din_port_info.get_width());
/* Top module Enable port -> BL Decoder Enable port */
add_module_bus_nets(module_manager,
top_module,
top_module, 0, en_port,
bl_decoder_module, 0, bl_decoder_en_port);
bl_decoder_module, curr_bl_decoder_instance_id, bl_decoder_en_port);
/* Top module Address port -> BL Decoder Address port */
add_module_bus_nets(module_manager,
top_module,
top_module, 0, bl_addr_port,
bl_decoder_module, 0, bl_decoder_addr_port);
bl_decoder_module, curr_bl_decoder_instance_id, bl_decoder_addr_port,
true);
/* Top module data_in port -> BL Decoder data_in port */
/* Top module data_in port -> BL Decoder data_in port:
* Note that each region has independent data_in connection from the top-level module
* The pin index is the configuration region index
*/
add_module_bus_nets(module_manager,
top_module,
top_module, 0, din_port,
bl_decoder_module, 0, bl_decoder_din_port);
bl_decoder_module, curr_bl_decoder_instance_id, bl_decoder_din_port);
ModuleNetId din_net = create_module_source_pin_net(module_manager, top_module,
top_module, 0,
din_port,
din_port_info.pins()[size_t(config_region)]);
VTR_ASSERT(ModuleNetId::INVALID() != din_net);
/* Add module nets from the top module to WL decoder's inputs */
/* Configure the net sink */
module_manager.add_module_net_sink(top_module, din_net, bl_decoder_module, curr_bl_decoder_instance_id, bl_decoder_din_port, bl_decoder_din_port_info.pins()[0]);
/**************************************************************
* Add module nets from the top module to WL decoder's inputs
*/
ModulePortId wl_decoder_en_port = module_manager.find_module_port(wl_decoder_module, std::string(DECODER_ENABLE_PORT_NAME));
BasicPort wl_decoder_en_port_info = module_manager.module_port(wl_decoder_module, wl_decoder_en_port);
@ -949,23 +1012,26 @@ void add_top_module_nets_cmos_memory_bank_config_bus(ModuleManager& module_manag
add_module_bus_nets(module_manager,
top_module,
top_module, 0, en_port,
wl_decoder_module, 0, wl_decoder_en_port);
wl_decoder_module, curr_wl_decoder_instance_id, wl_decoder_en_port);
/* Top module Address port -> WL Decoder Address port */
add_module_bus_nets(module_manager,
top_module,
top_module, 0, wl_addr_port,
wl_decoder_module, 0, wl_decoder_addr_port);
wl_decoder_module, curr_wl_decoder_instance_id, wl_decoder_addr_port,
true);
/* Add nets from BL data out to each configurable child */
/**************************************************************
* Add nets from BL data out to each configurable child
*/
size_t cur_bl_index = 0;
ModulePortId bl_decoder_dout_port = module_manager.find_module_port(bl_decoder_module, std::string(DECODER_DATA_OUT_PORT_NAME));
BasicPort bl_decoder_dout_port_info = module_manager.module_port(bl_decoder_module, bl_decoder_dout_port);
for (size_t child_id = 0; child_id < module_manager.configurable_children(top_module).size(); ++child_id) {
ModuleId child_module = module_manager.configurable_children(top_module)[child_id];
size_t child_instance = module_manager.configurable_child_instances(top_module)[child_id];
for (size_t child_id = 0; child_id < module_manager.region_configurable_children(top_module, config_region).size(); ++child_id) {
ModuleId child_module = module_manager.region_configurable_children(top_module, config_region)[child_id];
size_t child_instance = module_manager.region_configurable_child_instances(top_module, config_region)[child_id];
/* Find the BL port */
ModulePortId child_bl_port = module_manager.find_module_port(child_module, std::string(MEMORY_BL_PORT_NAME));
@ -976,10 +1042,12 @@ void add_top_module_nets_cmos_memory_bank_config_bus(ModuleManager& module_manag
* It should be the residual when divided by the number of BLs
*/
size_t bl_pin_id = std::floor(cur_bl_index / num_bls);
if (!(bl_pin_id < bl_decoder_dout_port_info.pins().size()))
VTR_ASSERT(bl_pin_id < bl_decoder_dout_port_info.pins().size());
/* Create net */
ModuleNetId net = create_module_source_pin_net(module_manager, top_module,
bl_decoder_module, 0,
bl_decoder_module, curr_bl_decoder_instance_id,
bl_decoder_dout_port,
bl_decoder_dout_port_info.pins()[bl_pin_id]);
VTR_ASSERT(ModuleNetId::INVALID() != net);
@ -993,15 +1061,17 @@ void add_top_module_nets_cmos_memory_bank_config_bus(ModuleManager& module_manag
}
}
/* Add nets from WL data out to each configurable child */
/**************************************************************
* Add nets from WL data out to each configurable child
*/
size_t cur_wl_index = 0;
ModulePortId wl_decoder_dout_port = module_manager.find_module_port(wl_decoder_module, std::string(DECODER_DATA_OUT_PORT_NAME));
BasicPort wl_decoder_dout_port_info = module_manager.module_port(wl_decoder_module, wl_decoder_dout_port);
for (size_t child_id = 0; child_id < module_manager.configurable_children(top_module).size(); ++child_id) {
ModuleId child_module = module_manager.configurable_children(top_module)[child_id];
size_t child_instance = module_manager.configurable_child_instances(top_module)[child_id];
for (size_t child_id = 0; child_id < module_manager.region_configurable_children(top_module, config_region).size(); ++child_id) {
ModuleId child_module = module_manager.region_configurable_children(top_module, config_region)[child_id];
size_t child_instance = module_manager.region_configurable_child_instances(top_module, config_region)[child_id];
/* Find the WL port */
ModulePortId child_wl_port = module_manager.find_module_port(child_module, std::string(MEMORY_WL_PORT_NAME));
@ -1015,7 +1085,7 @@ void add_top_module_nets_cmos_memory_bank_config_bus(ModuleManager& module_manag
/* Create net */
ModuleNetId net = create_module_source_pin_net(module_manager, top_module,
wl_decoder_module, 0,
wl_decoder_module, curr_wl_decoder_instance_id,
wl_decoder_dout_port,
wl_decoder_dout_port_info.pins()[wl_pin_id]);
VTR_ASSERT(ModuleNetId::INVALID() != net);
@ -1029,11 +1099,24 @@ void add_top_module_nets_cmos_memory_bank_config_bus(ModuleManager& module_manag
}
}
/* Add the BL and WL decoders to the end of configurable children list
/**************************************************************
* Add the BL and WL decoders to the end of configurable children list
* Note: this MUST be done after adding all the module nets to other regular configurable children
*/
module_manager.add_configurable_child(top_module, bl_decoder_module, 0);
module_manager.add_configurable_child(top_module, wl_decoder_module, 0);
module_manager.add_configurable_child(top_module, bl_decoder_module, curr_bl_decoder_instance_id);
module_manager.add_configurable_child_to_region(top_module,
config_region,
bl_decoder_module,
curr_bl_decoder_instance_id,
module_manager.configurable_children(top_module).size() - 1);
module_manager.add_configurable_child(top_module, wl_decoder_module, curr_wl_decoder_instance_id);
module_manager.add_configurable_child_to_region(top_module,
config_region,
wl_decoder_module,
curr_wl_decoder_instance_id,
module_manager.configurable_children(top_module).size() - 1);
}
}
/********************************************************************
@ -1203,7 +1286,7 @@ void add_top_module_nets_cmos_memory_config_bus(ModuleManager& module_manager,
DecoderLibrary& decoder_lib,
const ModuleId& parent_module,
const ConfigProtocol& config_protocol,
const size_t& num_config_bits) {
const vtr::vector<ConfigRegionId, size_t>& num_config_bits) {
switch (config_protocol.type()) {
case CONFIG_MEM_STANDALONE:
add_module_nets_cmos_flatten_memory_config_bus(module_manager, parent_module,
@ -1265,7 +1348,7 @@ void add_top_module_nets_memory_config_bus(ModuleManager& module_manager,
const ModuleId& parent_module,
const ConfigProtocol& config_protocol,
const e_circuit_model_design_tech& mem_tech,
const size_t& num_config_bits) {
const vtr::vector<ConfigRegionId, size_t>& num_config_bits) {
vtr::ScopedStartFinishTimer timer("Add module nets for configuration buses");

4
openfpga/src/fabric/build_top_module_memory.h
View File

@ -57,14 +57,14 @@ void add_top_module_sram_ports(ModuleManager& module_manager,
const CircuitLibrary& circuit_lib,
const CircuitModelId& sram_model,
const ConfigProtocol& config_protocol,
const size_t& num_config_bits);
const vtr::vector<ConfigRegionId, size_t>& num_config_bits);
void add_top_module_nets_memory_config_bus(ModuleManager& module_manager,
DecoderLibrary& decoder_lib,
const ModuleId& parent_module,
const ConfigProtocol& config_protocol,
const e_circuit_model_design_tech& mem_tech,
const size_t& num_config_bits);
const vtr::vector<ConfigRegionId, size_t>& num_config_bits);
} /* end namespace openfpga */

53
openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp
View File

@ -58,7 +58,6 @@ void rec_build_module_fabric_dependent_chain_bitstream(const BitstreamManager& b
/* Find the child block that matches the instance name! */
ConfigBlockId child_block = bitstream_manager.find_child_block(parent_block, instance_name);
/* We must have one valid block id! */
if (true != bitstream_manager.valid_block_id(child_block))
VTR_ASSERT(true == bitstream_manager.valid_block_id(child_block));
/* Go recursively */
@ -79,7 +78,6 @@ void rec_build_module_fabric_dependent_chain_bitstream(const BitstreamManager& b
/* Find the child block that matches the instance name! */
ConfigBlockId child_block = bitstream_manager.find_child_block(parent_block, instance_name);
/* We must have one valid block id! */
if (true != bitstream_manager.valid_block_id(child_block))
VTR_ASSERT(true == bitstream_manager.valid_block_id(child_block));
/* Go recursively */
@ -126,6 +124,7 @@ void rec_build_module_fabric_dependent_memory_bank_bitstream(const BitstreamMana
const ModuleManager& module_manager,
const ModuleId& top_module,
const ModuleId& parent_module,
const ConfigRegionId& config_region,
const size_t& bl_addr_size,
const size_t& wl_addr_size,
const size_t& num_bls,
@ -138,11 +137,16 @@ void rec_build_module_fabric_dependent_memory_bank_bitstream(const BitstreamMana
* we dive to the next level first!
*/
if (0 < bitstream_manager.block_children(parent_block).size()) {
/* For top module, we will skip the two decoders at the end of the configurable children list */
/* For top module:
* - Use regional configurable children
* - we will skip the two decoders at the end of the configurable children list
*/
std::vector<ModuleId> configurable_children = module_manager.configurable_children(parent_module);
size_t num_configurable_children = configurable_children.size();
if (parent_module == top_module) {
configurable_children = module_manager.region_configurable_children(parent_module, config_region);
VTR_ASSERT(2 <= configurable_children.size());
num_configurable_children -= 2;
}
@ -157,6 +161,10 @@ void rec_build_module_fabric_dependent_memory_bank_bitstream(const BitstreamMana
for (size_t child_id = 0; child_id < num_configurable_children; ++child_id) {
ModuleId child_module = configurable_children[child_id];
size_t child_instance = module_manager.configurable_child_instances(parent_module)[child_id];
if (parent_module == top_module) {
child_instance = module_manager.region_configurable_child_instances(parent_module, config_region)[child_id];
}
/* Get the instance name and ensure it is not empty */
std::string instance_name = module_manager.instance_name(parent_module, child_module, child_instance);
@ -169,6 +177,7 @@ void rec_build_module_fabric_dependent_memory_bank_bitstream(const BitstreamMana
/* Go recursively */
rec_build_module_fabric_dependent_memory_bank_bitstream(bitstream_manager, child_block,
module_manager, top_module, child_module,
config_region,
bl_addr_size, wl_addr_size,
num_bls, num_wls,
cur_mem_index,
@ -451,30 +460,14 @@ void build_module_fabric_dependent_bitstream(const ConfigProtocol& config_protoc
break;
}
case CONFIG_MEM_MEMORY_BANK: {
size_t cur_mem_index = 0;
/* Find BL address port size */
/* Find global BL address port size */
ModulePortId bl_addr_port = module_manager.find_module_port(top_module, std::string(DECODER_BL_ADDRESS_PORT_NAME));
BasicPort bl_addr_port_info = module_manager.module_port(top_module, bl_addr_port);
/* Find WL address port size */
/* Find global WL address port size */
ModulePortId wl_addr_port = module_manager.find_module_port(top_module, std::string(DECODER_WL_ADDRESS_PORT_NAME));
BasicPort wl_addr_port_info = module_manager.module_port(top_module, wl_addr_port);
/* Find BL and WL decoders which are the last two configurable children*/
std::vector<ModuleId> configurable_children = module_manager.configurable_children(top_module);
VTR_ASSERT(2 <= configurable_children.size());
ModuleId bl_decoder_module = configurable_children[configurable_children.size() - 2];
VTR_ASSERT(0 == module_manager.configurable_child_instances(top_module)[configurable_children.size() - 2]);
ModuleId wl_decoder_module = configurable_children[configurable_children.size() - 1];
VTR_ASSERT(0 == module_manager.configurable_child_instances(top_module)[configurable_children.size() - 1]);
ModulePortId bl_port = module_manager.find_module_port(bl_decoder_module, std::string(DECODER_DATA_OUT_PORT_NAME));
BasicPort bl_port_info = module_manager.module_port(bl_decoder_module, bl_port);
ModulePortId wl_port = module_manager.find_module_port(wl_decoder_module, std::string(DECODER_DATA_OUT_PORT_NAME));
BasicPort wl_port_info = module_manager.module_port(wl_decoder_module, wl_port);
/* Reserve bits before build-up */
fabric_bitstream.set_use_address(true);
fabric_bitstream.set_use_wl_address(true);
@ -482,13 +475,27 @@ void build_module_fabric_dependent_bitstream(const ConfigProtocol& config_protoc
fabric_bitstream.set_wl_address_length(wl_addr_port_info.get_width());
fabric_bitstream.reserve_bits(bitstream_manager.num_bits());
/* TODO: Currently only support 1 region. Will expand later! */
VTR_ASSERT(1 == module_manager.regions(top_module).size());
size_t cur_mem_index = 0;
/* Build bitstreams by region */
for (const ConfigRegionId& config_region : module_manager.regions(top_module)) {
/* Find port information for local BL and WL decoder in this region */
std::vector<ModuleId> configurable_children = module_manager.region_configurable_children(top_module, config_region);
VTR_ASSERT(2 <= configurable_children.size());
ModuleId bl_decoder_module = configurable_children[configurable_children.size() - 2];
ModuleId wl_decoder_module = configurable_children[configurable_children.size() - 1];
ModulePortId bl_port = module_manager.find_module_port(bl_decoder_module, std::string(DECODER_DATA_OUT_PORT_NAME));
BasicPort bl_port_info = module_manager.module_port(bl_decoder_module, bl_port);
ModulePortId wl_port = module_manager.find_module_port(wl_decoder_module, std::string(DECODER_DATA_OUT_PORT_NAME));
BasicPort wl_port_info = module_manager.module_port(wl_decoder_module, wl_port);
/* Build the bitstream for all the blocks in this region */
FabricBitRegionId fabric_bitstream_region = fabric_bitstream.add_region();
rec_build_module_fabric_dependent_memory_bank_bitstream(bitstream_manager, top_block,
module_manager, top_module, top_module,
config_region,
bl_addr_port_info.get_width(),
wl_addr_port_info.get_width(),
bl_port_info.get_width(),

85
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
View File

@ -1517,6 +1517,7 @@ void print_verilog_top_testbench_memory_bank_bitstream(std::fstream& fp,
fp << ";";
fp << std::endl;
fp << "\t\t";
fp << generate_verilog_port_constant_values(wl_addr_port, initial_wl_addr_values);
fp << ";";
fp << std::endl;
@ -1528,38 +1529,88 @@ void print_verilog_top_testbench_memory_bank_bitstream(std::fstream& fp,
fp << std::endl;
/* Attention: the configuration chain protcol requires the last configuration bit is fed first
* We will visit the fabric bitstream in a reverse way
/* Reorganize the fabric bitstream by the same address across regions:
* This is due to that the length of fabric bitstream could be different in each region.
* Template:
* <bl_address> <wl_address> <din_values_from_different_regions>
* An example:
* 000000 00000 1011
*
* Note: the std::map may cause large memory footprint for large bitstream databases!
*/
for (const FabricBitId& bit_id : fabric_bitstream.bits()) {
/* When fast configuration is enabled, we skip zero data_in values */
if ((true == fast_configuration)
&& (bit_value_to_skip == fabric_bitstream.bit_din(bit_id))) {
std::map<std::pair<std::string, std::string>, std::vector<bool>> fabric_bits_by_addr;
for (const FabricBitRegionId& region : fabric_bitstream.regions()) {
for (const FabricBitId& bit_id : fabric_bitstream.region_bits(region)) {
/* Create string for BL address */
VTR_ASSERT(bl_addr_port.get_width() == fabric_bitstream.bit_bl_address(bit_id).size());
std::string bl_addr_str;
for (const char& addr_bit : fabric_bitstream.bit_bl_address(bit_id)) {
bl_addr_str.push_back(addr_bit);
}
/* Create string for WL address */
VTR_ASSERT(wl_addr_port.get_width() == fabric_bitstream.bit_wl_address(bit_id).size());
std::string wl_addr_str;
for (const char& addr_bit : fabric_bitstream.bit_wl_address(bit_id)) {
wl_addr_str.push_back(addr_bit);
}
/* Place the config bit */
auto result = fabric_bits_by_addr.find(std::make_pair(bl_addr_str, wl_addr_str));
if (result == fabric_bits_by_addr.end()) {
/* This is a new bit, resize the vector to the number of regions
* and deposit '0' to all the bits
*/
fabric_bits_by_addr[std::make_pair(bl_addr_str, wl_addr_str)] = std::vector<bool>(fabric_bitstream.regions().size(), false);
fabric_bits_by_addr[std::make_pair(bl_addr_str, wl_addr_str)][size_t(region)] = fabric_bitstream.bit_din(bit_id);
} else {
VTR_ASSERT_SAFE(result != fabric_bits_by_addr.end());
result->second[size_t(region)] = fabric_bitstream.bit_din(bit_id);
}
}
}
for (const auto& addr_din_pair : fabric_bits_by_addr) {
/* When fast configuration is enabled,
* the rule to skip any configuration bit should consider the whole data input values.
* Only all the bits in the din port match the value to be skipped,
* the programming cycle can be skipped!
*/
if (true == fast_configuration) {
bool skip_curr_bits = true;
for (const bool& bit : addr_din_pair.second) {
if (bit_value_to_skip != bit) {
skip_curr_bits = false;
break;
}
}
if (true == skip_curr_bits) {
continue;
}
}
fp << "\t\t" << std::string(TOP_TESTBENCH_PROG_TASK_NAME);
fp << "(" << bl_addr_port.get_width() << "'b";
VTR_ASSERT(bl_addr_port.get_width() == fabric_bitstream.bit_bl_address(bit_id).size());
for (const char& addr_bit : fabric_bitstream.bit_bl_address(bit_id)) {
fp << addr_bit;
}
VTR_ASSERT(bl_addr_port.get_width() == addr_din_pair.first.first.length());
fp << addr_din_pair.first.first;
fp << ", ";
fp << wl_addr_port.get_width() << "'b";
VTR_ASSERT(wl_addr_port.get_width() == fabric_bitstream.bit_wl_address(bit_id).size());
for (const char& addr_bit : fabric_bitstream.bit_wl_address(bit_id)) {
fp << addr_bit;
}
VTR_ASSERT(wl_addr_port.get_width() == addr_din_pair.first.second.length());
fp << addr_din_pair.first.second;
fp << ", ";
fp <<"1'b";
if (true == fabric_bitstream.bit_din(bit_id)) {
fp << din_port.get_width() << "'b";
VTR_ASSERT(din_port.get_width() == addr_din_pair.second.size());
for (const bool& din_value : addr_din_pair.second) {
if (true == din_value) {
fp << "1";
} else {
VTR_ASSERT(false == fabric_bitstream.bit_din(bit_id));
VTR_ASSERT(false == din_value);
fp << "0";
}
}
fp << ");" << std::endl;
}

21
openfpga/src/utils/module_manager_utils.cpp
View File

@ -1793,6 +1793,16 @@ ModuleNetId create_module_source_pin_net(ModuleManager& module_manager,
* - des_module should be the cur_module or a child of it
* - src_instance should be valid and des_instance should be valid as well
* - src port size should match the des port size
*
* Power options:
* - align_to_lsb: This is by default turned off!
* When enabled, the source and destination ports
* will be connected pin-by-pin starting from
* the Least Significant Bit (LSB)
* The source and destination ports are not required
* to be same in sizes.
* BE CAREFUL! This may cause dangling pins!
* Use when you know what you are doing!
*******************************************************************/
void add_module_bus_nets(ModuleManager& module_manager,
const ModuleId& cur_module_id,
@ -1801,7 +1811,8 @@ void add_module_bus_nets(ModuleManager& module_manager,
const ModulePortId& src_module_port_id,
const ModuleId& des_module_id,
const size_t& des_instance_id,
const ModulePortId& des_module_port_id) {
const ModulePortId& des_module_port_id,
const bool& align_to_lsb) {
VTR_ASSERT(true == module_manager.valid_module_id(cur_module_id));
VTR_ASSERT(true == module_manager.valid_module_id(src_module_id));
@ -1825,7 +1836,8 @@ void add_module_bus_nets(ModuleManager& module_manager,
const BasicPort& src_port = module_manager.module_port(src_module_id, src_module_port_id);
const BasicPort& des_port = module_manager.module_port(des_module_id, des_module_port_id);
if (src_port.get_width() != des_port.get_width()) {
if ( (false == align_to_lsb)
&& (src_port.get_width() != des_port.get_width())) {
VTR_LOGF_ERROR(__FILE__, __LINE__,
"Unmatched port size: src_port %s is %lu while des_port %s is %lu!\n",
src_port.get_name().c_str(),
@ -1837,6 +1849,11 @@ void add_module_bus_nets(ModuleManager& module_manager,
/* Create a net for each pin */
for (size_t pin_id = 0; pin_id < src_port.pins().size(); ++pin_id) {
/* Create net only when des_port has a valid pin! */
if (pin_id >= des_port.pins().size()) {
continue;
}
ModuleNetId net = create_module_source_pin_net(module_manager, cur_module_id,
src_module_id, src_instance_id,
src_module_port_id, src_port.pins()[pin_id]);

3
openfpga/src/utils/module_manager_utils.h
View File

@ -165,7 +165,8 @@ void add_module_bus_nets(ModuleManager& module_manager,
const ModulePortId& src_module_port_id,
const ModuleId& des_module_id,
const size_t& des_instance_id,
const ModulePortId& des_module_port_id);
const ModulePortId& des_module_port_id,
const bool& align_to_lsb = false);
} /* end namespace openfpga */