Merge pull request #1028 from lnis-uofu/xt_debug_build

More build tests: debug and no warnings

.github/workflows/build.yml

@@ -263,6 +263,102 @@ jobs:
         run: |
           make all BUILD_TYPE=$BUILD_TYPE 
 
+  debug_build:
+    # Prevents from running on forks where no custom runners are available
+    needs: change_detect
+    if: ${{ fromJSON(needs.change_detect.outputs.source_modified) }} && ${{ github.repository_owner == 'lnis-uofu' }}
+    name: ${{ matrix.config.name }}
+    runs-on: [self-hosted, Linux, X64, eda_xt]
+    strategy:
+      fail-fast: false
+      matrix:
+        config:
+          - name: "Debug Build (Ubuntu 22.04)"
+            cc: gcc-11
+            cxx: g++-11
+            build_type: debug
+            cores: 4
+    # Define the steps to run the build job
+    env:
+      CC: ${{ matrix.config.cc }}
+      CXX: ${{ matrix.config.cxx }}
+    steps:
+      - name: Cancel previous
+        uses: styfle/cancel-workflow-action@0.9.1
+        with:
+          access_token: ${{ github.token }}
+          
+      - name: Checkout OpenFPGA repo
+        uses: actions/checkout@v2
+        with:
+          submodules: true
+
+      - name: Dump tool versions
+        run: |
+          cmake --version
+          ${CC} --version
+          ${CXX} --version
+
+      - uses: hendrikmuhs/ccache-action@v1
+
+      - name: Build
+        shell: bash
+        run: |
+          make all BUILD_TYPE=${{ matrix.config.build_type }} -j ${{ matrix.config.cores }}
+
+      - name: Quick Test
+        shell: bash
+        run: |
+          source openfpga.sh && run-task compilation_verification --debug --show_thread_logs
+
+  no_warning_build:
+    # Prevents from running on forks where no custom runners are available
+    needs: change_detect
+    if: ${{ fromJSON(needs.change_detect.outputs.source_modified) }} && ${{ github.repository_owner == 'lnis-uofu' }}
+    name: ${{ matrix.config.name }}
+    runs-on: [self-hosted, Linux, X64, eda_xt]
+    strategy:
+      fail-fast: false
+      matrix:
+        config:
+          - name: "No-warning Build (Ubuntu 22.04)"
+            cc: gcc-11
+            cxx: g++-11
+            build_type: release
+            cores: 4
+    # Define the steps to run the build job
+    env:
+      CC: ${{ matrix.config.cc }}
+      CXX: ${{ matrix.config.cxx }}
+    steps:
+      - name: Cancel previous
+        uses: styfle/cancel-workflow-action@0.9.1
+        with:
+          access_token: ${{ github.token }}
+          
+      - name: Checkout OpenFPGA repo
+        uses: actions/checkout@v2
+        with:
+          submodules: true
+
+      - name: Dump tool versions
+        run: |
+          cmake --version
+          ${CC} --version
+          ${CXX} --version
+
+      - uses: hendrikmuhs/ccache-action@v1
+
+      - name: Build
+        shell: bash
+        run: |
+          make all BUILD_TYPE=${{ matrix.config.build_type }} -j ${{ matrix.config.cores }} CMAKE_FLAGS="-DOPENFPGA_ENABLE_STRICT_COMPILE=ON"
+
+      - name: Quick Test
+        shell: bash
+        run: |
+          source openfpga.sh && run-task compilation_verification --debug --show_thread_logs
+
   docker_distribution:
     name: Build docker image for distribution
     runs-on: ubuntu-20.04

CMakeLists.txt

@@ -70,6 +70,7 @@ option(OPENFPGA_WITH_YOSYS_PLUGIN "Enable building Yosys plugin" ON)
 option(OPENFPGA_WITH_TEST "Enable testing build for codebase. Once enabled, make test can be run" ON)
 option(OPENFPGA_WITH_VERSION "Enable version always-up-to-date when building codebase. Disable only when you do not care an accurate version number" ON)
 option(OPENFPGA_WITH_SWIG "Enable SWIG interface when building codebase. Disable when you do not need high-level interfaces, such as Tcl/Python" ON)
+option(OPENFPGA_ENABLE_STRICT_COMPILE "Specifies whether compiler warnings should be treated as errors (e.g. -Werror)" OFF)
 
 # Options pass on to VTR
 set(WITH_ABC ON CACHE BOOL "Enable building ABC in Verilog-to-Routing")
@@ -83,6 +84,8 @@ set(WITH_YOSYS OFF CACHE BOOL "Enable building Yosys in Verilog-to-Routing")
 set(ODIN_YOSYS OFF CACHE BOOL "Enable building odin with yosys in Verilog-to-Routing")
 set(YOSYS_SV_UHDM_PLUGIN OFF CACHE BOOL "Enable building and installing Yosys SystemVerilog and UHDM plugins in Verilog-to-Routing")
 set(VTR_ENABLE_VERSION ${OPENFPGA_WITH_VERSION} CACHE BOOL "Enable version always-up-to-date when building codebase. Disable only when you do not care an accurate version number")
+# TODO: OpenFPGA and VPR has different requirements on no-warning build, e.g., on OS and compiler versions
+#set(VTR_ENABLE_STRICT_COMPILE ${OPENFPGA_ENABLE_STRICT_COMPILE} CACHE BOOL "Specifies whether compiler warnings should be treated as errors (e.g. -Werror)")
 
 # TCL file/lib required to link with SWIG generated wrapper
 if (OPENFPGA_WITH_SWIG)

Makefile

@@ -62,8 +62,8 @@ checkout:
 
 prebuild:
 # Run cmake to generate Makefile under the build directory, before compilation
-	@mkdir -p ${BUILD_DIR}
-	echo "cd ${BUILD_DIR} && ${CMAKE_COMMAND} ${CMAKE_FLAGS} ${SOURCE_DIR}"
+	@mkdir -p ${BUILD_DIR} && \
+	echo "cd ${BUILD_DIR} && ${CMAKE_COMMAND} ${CMAKE_FLAGS} ${SOURCE_DIR}" && \
 	cd ${BUILD_DIR} && ${CMAKE_COMMAND} ${CMAKE_FLAGS} ${SOURCE_DIR}
 
 compile: prebuild

docs/source/tutorials/getting_started/compile.rst

@@ -78,6 +78,7 @@ The following options are available for a custom build
   - ``DOPENFPGA_WITH_YOSYS_PLUGIN=[ON|OFF]``: Enable/Disable the build of yosys-plugin.
   - ``DOPENFPGA_WITH_VERSION=[ON|OFF]``: Enable/Disable the build of version number. When disabled, version number will be displayed as an empty string.
   - ``DOPENFPGA_WITH_SWIG=[ON|OFF]``: Enable/Disable the build of SWIG, which is required for integrating to high-level interface.
+  - ``OPENFPGA_ENABLE_STRICT_COMPILE=[ON|OFF]``: Specifies whether compiler warnings should be treated as errors (e.g. -Werror)
 
 .. warning:: By default, only required modules in *Verilog-to-Routing* (VTR) is enabled. On other words, ``abc``, ``odin``, ``yosys`` and other add-ons inside VTR are not built. If you want to enable them, please look into the dedicated options of CMake scripts.  
 

openfpga/CMakeLists.txt

@@ -47,6 +47,24 @@ target_link_libraries(libopenfpga
 add_executable(openfpga ${EXEC_SOURCE})
 target_link_libraries(openfpga libopenfpga)
 
+if (OPENFPGA_ENABLE_STRICT_COMPILE)
+    message(STATUS "OpenFPGA: building with strict flags")
+
+    set(OPENFPGA_STRICT_COMPILE_FLAGS_TO_CHECK
+        #GCC-like
+        "-Werror"
+        # due to the pointer hackery in timing_driven_route_structs and BinaryHeap.heap_
+        "-Wno-error=free-nonheap-object"
+        )
+
+    foreach(flag ${OPENFPGA_STRICT_COMPILE_FLAGS_TO_CHECK})
+        message(STATUS "\tAdding CXX flag: ${flag}")
+        target_compile_options(libopenfpga PRIVATE ${flag})
+        target_compile_options(openfpga PRIVATE ${flag})
+        target_link_libraries(openfpga ${flag})
+    endforeach()
+endif()
+
 #Suppress IPO link warnings if IPO is enabled
 get_target_property(OPENFPGA_USES_IPO openfpga INTERPROCEDURAL_OPTIMIZATION)
 if (OPENFPGA_USES_IPO)

openfpga/src/annotation/annotate_clustering.cpp

@@ -18,7 +18,7 @@ namespace openfpga {
  * up-to-date
  */
 bool annotate_post_routing_cluster_sync_results(
-  const DeviceContext& device_ctx, const ClusteringContext& clustering_ctx,
+  const ClusteringContext& clustering_ctx,
   VprClusteringAnnotation& clustering_annotation) {
   VTR_LOG(
     "Building annotation for post-routing and clustering synchornization "

openfpga/src/annotation/annotate_clustering.h

@@ -15,7 +15,7 @@
 namespace openfpga {
 
 bool annotate_post_routing_cluster_sync_results(
-  const DeviceContext& device_ctx, const ClusteringContext& clustering_ctx,
+  const ClusteringContext& clustering_ctx,
   VprClusteringAnnotation& clustering_annotation);
 
 } /* end namespace openfpga */

openfpga/src/base/openfpga_link_arch_template.h

@@ -131,7 +131,7 @@ int link_arch_template(T& openfpga_ctx, const Command& cmd,
   /* Annotate clustering results */
   if (CMD_EXEC_FATAL_ERROR ==
       annotate_post_routing_cluster_sync_results(
-        g_vpr_ctx.device(), g_vpr_ctx.clustering(),
+        g_vpr_ctx.clustering(),
         openfpga_ctx.mutable_vpr_clustering_annotation())) {
     return CMD_EXEC_FATAL_ERROR;
   }

openfpga/src/fpga_verilog/verilog_top_testbench.cpp

@@ -696,7 +696,7 @@ static void print_verilog_top_testbench_benchmark_clock_ports(
   /* Create a clock port if the benchmark have one but not in the default name!
    * We will wire the clock directly to the operating clock directly
    */
-  for (const std::string clock_port_name : clock_port_names) {
+  for (std::string clock_port_name : clock_port_names) {
     if (0 == clock_port_name.compare(default_clock_port.get_name())) {
       continue;
     }

openfpga/src/utils/lut_utils.cpp

@@ -451,8 +451,8 @@ std::vector<bool> build_frac_lut_bitstream(
   std::vector<bool> lut_bitstream(lut_mux_graph.num_inputs(),
                                   default_sram_bit_value);
 
-  for (const std::pair<const t_pb_graph_pin*, AtomNetlist::TruthTable>&
-         element : truth_tables) {
+  for (std::pair<const t_pb_graph_pin*, AtomNetlist::TruthTable> element :
+       truth_tables) {
     /* Find the corresponding circuit model output port and assoicated
      * lut_output_mask */
     CircuitPortId lut_model_output_port =