adapt tileable routing channel detail builder
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tangxifan
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6e83154703
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/************************************************************************
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* This file contains a builder for the ChanNodeDetails data structure
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* Different from VPR rr_graph builders, this builder aims to create a
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* highly regular routing channel. Thus, it is called tileable,
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* which brings significant advantage in producing large FPGA fabrics.
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***********************************************************************/
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#include <vector>
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#include <algorithm>
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/* Headers from vtrutil library */
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#include "vtr_assert.h"
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#include "vtr_log.h"
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#include "tileable_chan_details_builder.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/************************************************************************
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* Generate the number of tracks for each types of routing segments
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* w.r.t. the frequency of each of segments and channel width
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* Note that if we dertermine the number of tracks per type using
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* chan_width * segment_frequency / total_freq may cause
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* The total track num may not match the chan_width,
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* therefore, we assign tracks one by one until we meet the frequency requirement
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* In this way, we can assign the number of tracks with repect to frequency
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***********************************************************************/
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static
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std::vector<size_t> get_num_tracks_per_seg_type(const size_t& chan_width,
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const std::vector<t_segment_inf>& segment_inf,
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const bool& use_full_seg_groups) {
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std::vector<size_t> result;
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std::vector<double> demand;
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/* Make sure a clean start */
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result.resize(segment_inf.size());
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demand.resize(segment_inf.size());
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/* Scale factor so we can divide by any length
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* and still use integers */
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/* Get the sum of frequency */
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size_t scale = 1;
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size_t freq_sum = 0;
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for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) {
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scale *= segment_inf[iseg].length;
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freq_sum += segment_inf[iseg].frequency;
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}
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size_t reduce = scale * freq_sum;
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/* Init assignments to 0 and set the demand values */
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/* Get the fraction of each segment type considering the frequency:
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* num_track_per_seg = chan_width * (freq_of_seg / sum_freq)
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*/
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for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) {
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result[iseg] = 0;
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demand[iseg] = scale * chan_width * segment_inf[iseg].frequency;
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if (true == use_full_seg_groups) {
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demand[iseg] /= segment_inf[iseg].length;
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}
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}
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/* check if the sum of num_tracks, matches the chan_width */
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/* Keep assigning tracks until we use them up */
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size_t assigned = 0;
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size_t size = 0;
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size_t imax = 0;
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while (assigned < chan_width) {
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/* Find current maximum demand */
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double max = 0;
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for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) {
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if (demand[iseg] > max) {
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imax = iseg;
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}
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max = std::max(demand[iseg], max);
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}
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/* Assign tracks to the type and reduce the types demand */
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size = (use_full_seg_groups ? segment_inf[imax].length : 1);
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demand[imax] -= reduce;
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result[imax] += size;
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assigned += size;
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}
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/* Undo last assignment if we were closer to goal without it */
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if ((assigned - chan_width) > (size / 2)) {
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result[imax] -= size;
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}
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return result;
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}
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/************************************************************************
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* Adapt the number of channel width to a tileable routing architecture
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***********************************************************************/
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int adapt_to_tileable_route_chan_width(const int& chan_width,
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const std::vector<t_segment_inf>& segment_infs) {
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int tileable_chan_width = 0;
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/* Estimate the number of segments per type by the given ChanW*/
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std::vector<size_t> num_tracks_per_seg_type = get_num_tracks_per_seg_type(chan_width,
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segment_infs,
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true); /* Force to use the full segment group */
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/* Sum-up the number of tracks */
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for (size_t iseg = 0; iseg < num_tracks_per_seg_type.size(); ++iseg) {
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tileable_chan_width += num_tracks_per_seg_type[iseg];
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}
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return tileable_chan_width;
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}
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/************************************************************************
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* Build details of routing tracks in a channel
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* The function will
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* 1. Assign the segments for each routing channel,
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* To be specific, for each routing track, we assign a routing segment.
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* The assignment is subject to users' specifications, such as
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* a. length of each type of segment
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* b. frequency of each type of segment.
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* c. routing channel width
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*
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* 2. The starting point of each segment in the channel will be assigned
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* For each segment group with same directionality (tracks have the same length),
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* every L track will be a starting point (where L denotes the length of segments)
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* In this case, if the number of tracks is not a multiple of L,
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* indeed we may have some <L segments. This can be considered as a side effect.
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* But still the rr_graph is tileable, which is the first concern!
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*
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* Here is a quick example of Length-4 wires in a W=12 routing channel
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* +---------------------------------------+--------------+
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* | Index | Direction | Starting Point | Ending Point |
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* +---------------------------------------+--------------+
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* | 0 | MUX--------> | Yes | No |
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* +---------------------------------------+--------------+
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* | 1 | <--------MUX | Yes | No |
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* +---------------------------------------+--------------+
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* | 2 | --------> | No | No |
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* +---------------------------------------+--------------+
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* | 3 | <-------- | No | No |
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* +---------------------------------------+--------------+
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* | 4 | --------> | No | No |
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* +---------------------------------------+--------------+
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* | 5 | <-------- | No | No |
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* +---------------------------------------+--------------+
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* | 7 | -------->MUX | No | Yes |
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* +---------------------------------------+--------------+
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* | 8 | MUX<-------- | No | Yes |
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* +---------------------------------------+--------------+
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* | 9 | MUX--------> | Yes | No |
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* +---------------------------------------+--------------+
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* | 10 | <--------MUX | Yes | No |
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* +---------------------------------------+--------------+
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* | 11 | -------->MUX | No | Yes |
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* +------------------------------------------------------+
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* | 12 | <-------- | No | No |
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* +------------------------------------------------------+
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*
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* 3. SPECIAL for fringes: TOP|RIGHT|BOTTOM|RIGHT
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* if device_side is NUM_SIDES, we assume this channel does not locate on borders
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* All segments will start and ends with no exception
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*
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* 4. IMPORTANT: we should be aware that channel width maybe different
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* in X-direction and Y-direction channels!!!
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* So we will load segment details for different channels
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***********************************************************************/
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ChanNodeDetails build_unidir_chan_node_details(const size_t& chan_width, const size_t& max_seg_length,
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const enum e_side& device_side,
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const std::vector<t_segment_inf>& segment_inf) {
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ChanNodeDetails chan_node_details;
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size_t actual_chan_width = chan_width;
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/* Correct the chan_width: it should be an even number */
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if (0 != actual_chan_width % 2) {
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actual_chan_width++; /* increment it to be even */
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}
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VTR_ASSERT(0 == actual_chan_width % 2);
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/* Reserve channel width */
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chan_node_details.reserve(chan_width);
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/* Return if zero width is forced */
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if (0 == actual_chan_width) {
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return chan_node_details;
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}
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/* Find the number of segments required by each group */
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std::vector<size_t> num_tracks = get_num_tracks_per_seg_type(actual_chan_width/2, segment_inf, false);
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/* Add node to ChanNodeDetails */
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size_t cur_track = 0;
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for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) {
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/* segment length will be set to maxium segment length if this is a longwire */
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size_t seg_len = segment_inf[iseg].length;
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if (true == segment_inf[iseg].longline) {
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seg_len = max_seg_length;
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}
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for (size_t itrack = 0; itrack < num_tracks[iseg]; ++itrack) {
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bool seg_start = false;
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bool seg_end = false;
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/* Every first track of a group of Length-N wires, we set a starting point */
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if (0 == itrack % seg_len) {
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seg_start = true;
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}
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/* Every last track of a group of Length-N wires or this is the last track in this group, we set an ending point */
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if ( (seg_len - 1 == itrack % seg_len)
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|| (itrack == num_tracks[iseg] - 1) ) {
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seg_end = true;
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}
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/* Since this is a unidirectional routing architecture,
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* Add a pair of tracks, 1 INC_DIRECTION track and 1 DEC_DIRECTION track
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*/
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chan_node_details.add_track(cur_track, INC_DIRECTION, iseg, seg_len, seg_start, seg_end);
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cur_track++;
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chan_node_details.add_track(cur_track, DEC_DIRECTION, iseg, seg_len, seg_start, seg_end);
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cur_track++;
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}
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}
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/* Check if all the tracks have been satisified */
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VTR_ASSERT(cur_track == actual_chan_width);
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/* If this is on the border of a device, segments should start */
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switch (device_side) {
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case TOP:
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case RIGHT:
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/* INC_DIRECTION should all end */
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chan_node_details.set_tracks_end(INC_DIRECTION);
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/* DEC_DIRECTION should all start */
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chan_node_details.set_tracks_start(DEC_DIRECTION);
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break;
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case BOTTOM:
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case LEFT:
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/* INC_DIRECTION should all start */
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chan_node_details.set_tracks_start(INC_DIRECTION);
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/* DEC_DIRECTION should all end */
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chan_node_details.set_tracks_end(DEC_DIRECTION);
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break;
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case NUM_SIDES:
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break;
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default:
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VTR_LOGF_ERROR(__FILE__, __LINE__,
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"Invalid device_side!\n");
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exit(1);
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}
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return chan_node_details;
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}
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} /* end namespace openfpga */
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@ -0,0 +1,26 @@
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#ifndef TILEABLE_CHAN_DETAILS_BUILDER_H
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#define TILEABLE_CHAN_DETAILS_BUILDER_H
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/********************************************************************
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* Include header files that are required by function declaration
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*******************************************************************/
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#include <vector>
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#include "physical_types.h"
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#include "chan_node_details.h"
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/********************************************************************
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* Function declaration
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*******************************************************************/
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/* begin namespace openfpga */
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namespace openfpga {
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int adapt_to_tileable_route_chan_width(const int& chan_width, const std::vector<t_segment_inf>& segment_inf);
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ChanNodeDetails build_unidir_chan_node_details(const size_t& chan_width, const size_t& max_seg_length,
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const e_side& device_side,
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const std::vector<t_segment_inf>& segment_inf);
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} /* end namespace openfpga */
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#endif
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