diff --git a/fpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml b/fpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml
deleted file mode 100644
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--- a/fpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml
+++ /dev/null
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diff --git a/fpga_flow/benchmarks/List/lattice_benchmark.txt b/fpga_flow/benchmarks/List/lattice_benchmark.txt
deleted file mode 100644
index 912818af7..000000000
--- a/fpga_flow/benchmarks/List/lattice_benchmark.txt
+++ /dev/null
@@ -1,2 +0,0 @@
-# Circuit Names, fixed routing channel width,
-PID/*.v, 120
\ No newline at end of file
diff --git a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/.gitignore b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/.gitignore
deleted file mode 100644
index 7e0debc3e..000000000
--- a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/.gitignore
+++ /dev/null
@@ -1,8 +0,0 @@
-# Ignore everything
-*
-# But descend into directories
-!*/
-!.gitignore
-# Recursively allow files under subtree
-!/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/**
-!/PID_Controller/**
diff --git a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/16x16bit_multiplier_pipelined.v b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/16x16bit_multiplier_pipelined.v
deleted file mode 100644
index 7e9f45680..000000000
--- a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/16x16bit_multiplier_pipelined.v
+++ /dev/null
@@ -1,1413 +0,0 @@
-/*16x16-bit multiplier
-Author: Zhu Xu
-Email: m99a1@yahoo.cn
-*/
-
-//Booth Encoder Array
-module booth_array(
-input [15:0]multiplier,
-output [7:0]zero,
-output [7:0]double,
-output [7:0]negation
-);
-
-booth_radix4 booth_radix4_0(
-{multiplier[1:0],1'b0},
-zero[0],
-double[0],
-negation[0]
-);
-
-booth_radix4 booth_radix4_1(
-multiplier[3:1],
-zero[1],
-double[1],
-negation[1]
-);
-
-booth_radix4 booth_radix4_2(
-multiplier[5:3],
-zero[2],
-double[2],
-negation[2]
-);
-booth_radix4 booth_radix4_3(
-multiplier[7:5],
-zero[3],
-double[3],
-negation[3]
-);
-
-booth_radix4 booth_radix4_4(
-multiplier[9:7],
-zero[4],
-double[4],
-negation[4]
-);
-
-booth_radix4 booth_radix4_5(
-multiplier[11:9],
-zero[5],
-double[5],
-negation[5]
-);
-booth_radix4 booth_radix4_6(
-multiplier[13:11],
-zero[6],
-double[6],
-negation[6]
-);
-
-booth_radix4 booth_radix4_7(
-multiplier[15:13],
-zero[7],
-double[7],
-negation[7]
-);
-
-endmodule
-
-/*partial product generator unit
-generate one 17-bit partial with inversed MSB without correction bit for negation
-*/
-module partial_product_gen(
-input [15:0]md, //multiplicand
-input zero,
-input double,
-input negation,
-output [16:0]pp
-);
-
-wire [15:0]nmd;
-assign nmd=negation?~md:md;
-
-wire [15:0]zmd;
-assign zmd=zero?0:nmd;
-
-assign pp=double?{~zmd[15],zmd[14:0],negation}:{~zmd[15],zmd[15:0]};
-
-endmodule
-
-module half_adder(
-input A,
-input B,
-output S,
-output carry
-);
-assign S=A^B;
-assign carry=A&B;
-endmodule
-
-module full_adder(
-input A,
-input B,
-input cin,
-output S,
-output cout
-);
-wire AB;
-assign AB=A&B;
-wire AxorB;
-assign AxorB=A^B;
-assign S=AxorB^cin;
-assign cout=AB|(AxorB&cin);
-endmodule
-
-module compressor42(
-input A,
-input B,
-input C,
-input D,
-input cin,
-output S,
-output carry,
-output cout
-);
-wire AB;
-assign AB=A&B;
-wire AxorB;
-assign AxorB=A^B;
-wire CD;
-assign CD=C&D;
-wire CxorD;
-assign CxorD=C^D;
-
-wire AxBxCxD=AxorB^CxorD;
-
-assign cout=AB|CD;
-assign carry=(AB&CD)|(AxorB&CxorD)|((AxBxCxD)&cin);
-
-assign S=AxBxCxD^cin;
-
-endmodule
-
-
-module multiplier_16x16bit_pipelined(
-input i_clk,
-input i_rst,
-input i_start,
-input [15:0]i_md,
-input [15:0]i_mr,
-output [31:0]o_product,
-output o_ready
-);
-/////////////////////////////////////////////////////////////stage 0///////////////////////////////////////////////////
-
-reg [15:0]md;
-reg [15:0]mr;
-reg stage_0_ready;
-
-always @(posedge i_clk or negedge i_rst)begin
- if(!i_rst)begin
- md<=0;
- mr<=0;
- stage_0_ready<=0;
- end
- else begin
- if(i_start)begin
- md<=i_md;
- mr<=i_mr;
- end
- stage_0_ready<=i_start;
- end
-
-end
-
-wire [7:0]zero;
-wire [7:0]double;
-wire [7:0]negation;
-
-booth_array booth_array_0(
-mr,
-zero,
-double,
-negation
-);
-
-
-//layer 0
-wire layer_0_w0[1:0];
-wire layer_0_w1;
-wire layer_0_w2[2:0];
-wire layer_0_w3[1:0];
-wire layer_0_w4[3:0];
-wire layer_0_w5[2:0];
-wire layer_0_w6[4:0];
-wire layer_0_w7[3:0];
-wire layer_0_w8[5:0];
-wire layer_0_w9[4:0];
-wire layer_0_w10[6:0];
-wire layer_0_w11[5:0];
-wire layer_0_w12[7:0];
-wire layer_0_w13[6:0];
-wire layer_0_w14[8:0];
-wire layer_0_w15[7:0];
-wire layer_0_w16[8:0];
-wire layer_0_w17[7:0];
-wire layer_0_w18[6:0];
-wire layer_0_w19[6:0];
-wire layer_0_w20[5:0];
-wire layer_0_w21[5:0];
-wire layer_0_w22[4:0];
-wire layer_0_w23[4:0];
-wire layer_0_w24[3:0];
-wire layer_0_w25[3:0];
-wire layer_0_w26[2:0];
-wire layer_0_w27[2:0];
-wire layer_0_w28[1:0];
-wire layer_0_w29[1:0];
-wire layer_0_w30;
-wire layer_0_w31;
-partial_product_gen partial_product_gen_0(
-md,
-zero[0],
-double[0],
-negation[0],
-{layer_0_w16[0],layer_0_w15[0],layer_0_w14[0],layer_0_w13[0],layer_0_w12[0],layer_0_w11[0],layer_0_w10[0],layer_0_w9[0],layer_0_w8[0],layer_0_w7[0],layer_0_w6[0],layer_0_w5[0],layer_0_w4[0],layer_0_w3[0],layer_0_w2[0],layer_0_w1,layer_0_w0[0]}
-);
-partial_product_gen partial_product_gen_1(
-md,
-zero[1],
-double[1],
-negation[1],
-{layer_0_w18[0],layer_0_w17[0],layer_0_w16[1],layer_0_w15[1],layer_0_w14[1],layer_0_w13[1],layer_0_w12[1],layer_0_w11[1],layer_0_w10[1],layer_0_w9[1],layer_0_w8[1],layer_0_w7[1],layer_0_w6[1],layer_0_w5[1],layer_0_w4[1],layer_0_w3[1],layer_0_w2[1]}
-);
-partial_product_gen partial_product_gen_2(
-md,
-zero[2],
-double[2],
-negation[2],
-{layer_0_w20[0],layer_0_w19[0],layer_0_w18[1],layer_0_w17[1],layer_0_w16[2],layer_0_w15[2],layer_0_w14[2],layer_0_w13[2],layer_0_w12[2],layer_0_w11[2],layer_0_w10[2],layer_0_w9[2],layer_0_w8[2],layer_0_w7[2],layer_0_w6[2],layer_0_w5[2],layer_0_w4[2]}
-);
-partial_product_gen partial_product_gen_3(
-md,
-zero[3],
-double[3],
-negation[3],
-{layer_0_w22[0],layer_0_w21[0],layer_0_w20[1],layer_0_w19[1],layer_0_w18[2],layer_0_w17[2],layer_0_w16[3],layer_0_w15[3],layer_0_w14[3],layer_0_w13[3],layer_0_w12[3],layer_0_w11[3],layer_0_w10[3],layer_0_w9[3],layer_0_w8[3],layer_0_w7[3],layer_0_w6[3]}
-);
-partial_product_gen partial_product_gen_4(
-md,
-zero[4],
-double[4],
-negation[4],
-{layer_0_w24[0],layer_0_w23[0],layer_0_w22[1],layer_0_w21[1],layer_0_w20[2],layer_0_w19[2],layer_0_w18[3],layer_0_w17[3],layer_0_w16[4],layer_0_w15[4],layer_0_w14[4],layer_0_w13[4],layer_0_w12[4],layer_0_w11[4],layer_0_w10[4],layer_0_w9[4],layer_0_w8[4]}
-);
-partial_product_gen partial_product_gen_5(
-md,
-zero[5],
-double[5],
-negation[5],
-{layer_0_w26[0],layer_0_w25[0],layer_0_w24[1],layer_0_w23[1],layer_0_w22[2],layer_0_w21[2],layer_0_w20[3],layer_0_w19[3],layer_0_w18[4],layer_0_w17[4],layer_0_w16[5],layer_0_w15[5],layer_0_w14[5],layer_0_w13[5],layer_0_w12[5],layer_0_w11[5],layer_0_w10[5]}
-);
-partial_product_gen partial_product_gen_6(
-md,
-zero[6],
-double[6],
-negation[6],
-{layer_0_w28[0],layer_0_w27[0],layer_0_w26[1],layer_0_w25[1],layer_0_w24[2],layer_0_w23[2],layer_0_w22[3],layer_0_w21[3],layer_0_w20[4],layer_0_w19[4],layer_0_w18[5],layer_0_w17[5],layer_0_w16[6],layer_0_w15[6],layer_0_w14[6],layer_0_w13[6],layer_0_w12[6]}
-);
-partial_product_gen partial_product_gen_7(
-md,
-zero[7],
-double[7],
-negation[7],
-{layer_0_w30,layer_0_w29[0],layer_0_w28[1],layer_0_w27[1],layer_0_w26[2],layer_0_w25[2],layer_0_w24[3],layer_0_w23[3],layer_0_w22[4],layer_0_w21[4],layer_0_w20[5],layer_0_w19[5],layer_0_w18[6],layer_0_w17[6],layer_0_w16[7],layer_0_w15[7],layer_0_w14[7]}
-);
-//correction for negation
-assign layer_0_w0[1]=negation[0];
-//sign extension
-assign layer_0_w16[8]=1;
-assign layer_0_w17[7]=1;
-//correction for negation
-assign layer_0_w2[2]=negation[1];
-//sign extension
-assign layer_0_w19[6]=1;
-//correction for negation
-assign layer_0_w4[3]=negation[2];
-//sign extension
-assign layer_0_w21[5]=1;
-//correction for negation
-assign layer_0_w6[4]=negation[3];
-//sign extension
-assign layer_0_w23[4]=1;
-//correction for negation
-assign layer_0_w8[5]=negation[4];
-//sign extension
-assign layer_0_w25[3]=1;
-//correction for negation
-assign layer_0_w10[6]=negation[5];
-//sign extension
-assign layer_0_w27[2]=1;
-//correction for negation
-assign layer_0_w12[7]=negation[6];
-//sign extension
-assign layer_0_w29[1]=1;
-//correction for negation
-assign layer_0_w14[8]=negation[7];
-//sign extension
-assign layer_0_w31=1;
-
-//layer 1
-wire layer_1_w0[1:0];
-wire layer_1_w1;
-wire layer_1_w2[2:0];
-wire layer_1_w3[1:0];
-wire layer_1_w4[1:0];
-wire layer_1_w5[1:0];
-wire layer_1_w6[1:0];
-wire layer_1_w7[3:0];
-wire layer_1_w8[2:0];
-wire layer_1_w9[2:0];
-wire layer_1_w10[4:0];
-wire layer_1_w11[3:0];
-wire layer_1_w12[3:0];
-wire layer_1_w13[5:0];
-wire layer_1_w14[4:0];
-wire layer_1_w15[4:0];
-wire layer_1_w16[5:0];
-wire layer_1_w17[4:0];
-wire layer_1_w18[5:0];
-wire layer_1_w19[4:0];
-wire layer_1_w20[3:0];
-wire layer_1_w21[3:0];
-wire layer_1_w22[2:0];
-wire layer_1_w23[2:0];
-wire layer_1_w24[3:0];
-wire layer_1_w25[2:0];
-wire layer_1_w26[1:0];
-wire layer_1_w27[1:0];
-wire layer_1_w28[2:0];
-wire layer_1_w29[1:0];
-wire layer_1_w30;
-wire layer_1_w31;
-assign layer_1_w0[0]=layer_0_w0[0];
-assign layer_1_w0[1]=layer_0_w0[1];
-assign layer_1_w1=layer_0_w1;
-assign layer_1_w2[0]=layer_0_w2[0];
-assign layer_1_w2[1]=layer_0_w2[1];
-assign layer_1_w2[2]=layer_0_w2[2];
-assign layer_1_w3[0]=layer_0_w3[0];
-assign layer_1_w3[1]=layer_0_w3[1];
-full_adder layer_1_full_adder_0(
-layer_0_w4[0],
-layer_0_w4[1],
-layer_0_w4[2],
-layer_1_w4[0],
-layer_1_w5[0]
-);
-assign layer_1_w4[1]=layer_0_w4[3];
-full_adder layer_1_full_adder_1(
-layer_0_w5[0],
-layer_0_w5[1],
-layer_0_w5[2],
-layer_1_w5[1],
-layer_1_w6[0]
-);
-compressor42 layer_1_compressor42_0(
-layer_0_w6[0],
-layer_0_w6[1],
-layer_0_w6[2],
-layer_0_w6[3],
-layer_0_w6[4],
-layer_1_w6[1],
-layer_1_w7[0],
-layer_1_w7[1]
-);
-full_adder layer_1_full_adder_2(
-layer_0_w7[0],
-layer_0_w7[1],
-layer_0_w7[2],
-layer_1_w7[2],
-layer_1_w8[0]
-);
-assign layer_1_w7[3]=layer_0_w7[3];
-compressor42 layer_1_compressor42_1(
-layer_0_w8[0],
-layer_0_w8[1],
-layer_0_w8[2],
-layer_0_w8[3],
-layer_0_w8[4],
-layer_1_w8[1],
-layer_1_w9[0],
-layer_1_w9[1]
-);
-assign layer_1_w8[2]=layer_0_w8[5];
-compressor42 layer_1_compressor42_2(
-layer_0_w9[0],
-layer_0_w9[1],
-layer_0_w9[2],
-layer_0_w9[3],
-layer_0_w9[4],
-layer_1_w9[2],
-layer_1_w10[0],
-layer_1_w10[1]
-);
-compressor42 layer_1_compressor42_3(
-layer_0_w10[0],
-layer_0_w10[1],
-layer_0_w10[2],
-layer_0_w10[3],
-layer_0_w10[4],
-layer_1_w10[2],
-layer_1_w11[0],
-layer_1_w11[1]
-);
-assign layer_1_w10[3]=layer_0_w10[5];
-assign layer_1_w10[4]=layer_0_w10[6];
-compressor42 layer_1_compressor42_4(
-layer_0_w11[0],
-layer_0_w11[1],
-layer_0_w11[2],
-layer_0_w11[3],
-layer_0_w11[4],
-layer_1_w11[2],
-layer_1_w12[0],
-layer_1_w12[1]
-);
-assign layer_1_w11[3]=layer_0_w11[5];
-compressor42 layer_1_compressor42_5(
-layer_0_w12[0],
-layer_0_w12[1],
-layer_0_w12[2],
-layer_0_w12[3],
-layer_0_w12[4],
-layer_1_w12[2],
-layer_1_w13[0],
-layer_1_w13[1]
-);
-full_adder layer_1_full_adder_3(
-layer_0_w12[5],
-layer_0_w12[6],
-layer_0_w12[7],
-layer_1_w12[3],
-layer_1_w13[2]
-);
-compressor42 layer_1_compressor42_6(
-layer_0_w13[0],
-layer_0_w13[1],
-layer_0_w13[2],
-layer_0_w13[3],
-layer_0_w13[4],
-layer_1_w13[3],
-layer_1_w14[0],
-layer_1_w14[1]
-);
-assign layer_1_w13[4]=layer_0_w13[5];
-assign layer_1_w13[5]=layer_0_w13[6];
-compressor42 layer_1_compressor42_7(
-layer_0_w14[0],
-layer_0_w14[1],
-layer_0_w14[2],
-layer_0_w14[3],
-layer_0_w14[4],
-layer_1_w14[2],
-layer_1_w15[0],
-layer_1_w15[1]
-);
-full_adder layer_1_full_adder_4(
-layer_0_w14[5],
-layer_0_w14[6],
-layer_0_w14[7],
-layer_1_w14[3],
-layer_1_w15[2]
-);
-assign layer_1_w14[4]=layer_0_w14[8];
-compressor42 layer_1_compressor42_8(
-layer_0_w15[0],
-layer_0_w15[1],
-layer_0_w15[2],
-layer_0_w15[3],
-layer_0_w15[4],
-layer_1_w15[3],
-layer_1_w16[0],
-layer_1_w16[1]
-);
-full_adder layer_1_full_adder_5(
-layer_0_w15[5],
-layer_0_w15[6],
-layer_0_w15[7],
-layer_1_w15[4],
-layer_1_w16[2]
-);
-compressor42 layer_1_compressor42_9(
-layer_0_w16[0],
-layer_0_w16[1],
-layer_0_w16[2],
-layer_0_w16[3],
-layer_0_w16[4],
-layer_1_w16[3],
-layer_1_w17[0],
-layer_1_w17[1]
-);
-full_adder layer_1_full_adder_6(
-layer_0_w16[5],
-layer_0_w16[6],
-layer_0_w16[7],
-layer_1_w16[4],
-layer_1_w17[2]
-);
-assign layer_1_w16[5]=layer_0_w16[8];
-compressor42 layer_1_compressor42_10(
-layer_0_w17[0],
-layer_0_w17[1],
-layer_0_w17[2],
-layer_0_w17[3],
-layer_0_w17[4],
-layer_1_w17[3],
-layer_1_w18[0],
-layer_1_w18[1]
-);
-full_adder layer_1_full_adder_7(
-layer_0_w17[5],
-layer_0_w17[6],
-layer_0_w17[7],
-layer_1_w17[4],
-layer_1_w18[2]
-);
-compressor42 layer_1_compressor42_11(
-layer_0_w18[0],
-layer_0_w18[1],
-layer_0_w18[2],
-layer_0_w18[3],
-layer_0_w18[4],
-layer_1_w18[3],
-layer_1_w19[0],
-layer_1_w19[1]
-);
-assign layer_1_w18[4]=layer_0_w18[5];
-assign layer_1_w18[5]=layer_0_w18[6];
-compressor42 layer_1_compressor42_12(
-layer_0_w19[0],
-layer_0_w19[1],
-layer_0_w19[2],
-layer_0_w19[3],
-layer_0_w19[4],
-layer_1_w19[2],
-layer_1_w20[0],
-layer_1_w20[1]
-);
-assign layer_1_w19[3]=layer_0_w19[5];
-assign layer_1_w19[4]=layer_0_w19[6];
-compressor42 layer_1_compressor42_13(
-layer_0_w20[0],
-layer_0_w20[1],
-layer_0_w20[2],
-layer_0_w20[3],
-layer_0_w20[4],
-layer_1_w20[2],
-layer_1_w21[0],
-layer_1_w21[1]
-);
-assign layer_1_w20[3]=layer_0_w20[5];
-compressor42 layer_1_compressor42_14(
-layer_0_w21[0],
-layer_0_w21[1],
-layer_0_w21[2],
-layer_0_w21[3],
-layer_0_w21[4],
-layer_1_w21[2],
-layer_1_w22[0],
-layer_1_w22[1]
-);
-assign layer_1_w21[3]=layer_0_w21[5];
-compressor42 layer_1_compressor42_15(
-layer_0_w22[0],
-layer_0_w22[1],
-layer_0_w22[2],
-layer_0_w22[3],
-layer_0_w22[4],
-layer_1_w22[2],
-layer_1_w23[0],
-layer_1_w23[1]
-);
-compressor42 layer_1_compressor42_16(
-layer_0_w23[0],
-layer_0_w23[1],
-layer_0_w23[2],
-layer_0_w23[3],
-layer_0_w23[4],
-layer_1_w23[2],
-layer_1_w24[0],
-layer_1_w24[1]
-);
-full_adder layer_1_full_adder_8(
-layer_0_w24[0],
-layer_0_w24[1],
-layer_0_w24[2],
-layer_1_w24[2],
-layer_1_w25[0]
-);
-assign layer_1_w24[3]=layer_0_w24[3];
-full_adder layer_1_full_adder_9(
-layer_0_w25[0],
-layer_0_w25[1],
-layer_0_w25[2],
-layer_1_w25[1],
-layer_1_w26[0]
-);
-assign layer_1_w25[2]=layer_0_w25[3];
-full_adder layer_1_full_adder_10(
-layer_0_w26[0],
-layer_0_w26[1],
-layer_0_w26[2],
-layer_1_w26[1],
-layer_1_w27[0]
-);
-full_adder layer_1_full_adder_11(
-layer_0_w27[0],
-layer_0_w27[1],
-layer_0_w27[2],
-layer_1_w27[1],
-layer_1_w28[0]
-);
-assign layer_1_w28[1]=layer_0_w28[0];
-assign layer_1_w28[2]=layer_0_w28[1];
-assign layer_1_w29[0]=layer_0_w29[0];
-assign layer_1_w29[1]=layer_0_w29[1];
-assign layer_1_w30=layer_0_w30;
-assign layer_1_w31=layer_0_w31;
-
-//layer 2
-wire [1:0]layer_2_w0;
-wire layer_2_w1;
-wire [2:0]layer_2_w2;
-wire [1:0]layer_2_w3;
-wire [1:0]layer_2_w4;
-wire [1:0]layer_2_w5;
-wire [1:0]layer_2_w6;
-wire [1:0]layer_2_w7;
-wire [1:0]layer_2_w8;
-wire [1:0]layer_2_w9;
-wire [1:0]layer_2_w10;
-wire [3:0]layer_2_w11;
-wire [2:0]layer_2_w12;
-wire [2:0]layer_2_w13;
-wire [2:0]layer_2_w14;
-wire [2:0]layer_2_w15;
-wire [3:0]layer_2_w16;
-wire [2:0]layer_2_w17;
-wire [3:0]layer_2_w18;
-wire [2:0]layer_2_w19;
-wire [3:0]layer_2_w20;
-wire [2:0]layer_2_w21;
-wire [1:0]layer_2_w22;
-wire [1:0]layer_2_w23;
-wire [2:0]layer_2_w24;
-wire [1:0]layer_2_w25;
-wire [2:0]layer_2_w26;
-wire [1:0]layer_2_w27;
-wire layer_2_w28;
-wire [2:0]layer_2_w29;
-wire layer_2_w30;
-wire layer_2_w31;
-assign layer_2_w0[0]=layer_1_w0[0];
-assign layer_2_w0[1]=layer_1_w0[1];
-assign layer_2_w1=layer_1_w1;
-assign layer_2_w2[0]=layer_1_w2[0];
-assign layer_2_w2[1]=layer_1_w2[1];
-assign layer_2_w2[2]=layer_1_w2[2];
-assign layer_2_w3[0]=layer_1_w3[0];
-assign layer_2_w3[1]=layer_1_w3[1];
-assign layer_2_w4[0]=layer_1_w4[0];
-assign layer_2_w4[1]=layer_1_w4[1];
-assign layer_2_w5[0]=layer_1_w5[0];
-assign layer_2_w5[1]=layer_1_w5[1];
-assign layer_2_w6[0]=layer_1_w6[0];
-assign layer_2_w6[1]=layer_1_w6[1];
-full_adder layer_2_full_adder_0(
-layer_1_w7[0],
-layer_1_w7[1],
-layer_1_w7[2],
-layer_2_w7[0],
-layer_2_w8[0]
-);
-assign layer_2_w7[1]=layer_1_w7[3];
-full_adder layer_2_full_adder_1(
-layer_1_w8[0],
-layer_1_w8[1],
-layer_1_w8[2],
-layer_2_w8[1],
-layer_2_w9[0]
-);
-full_adder layer_2_full_adder_2(
-layer_1_w9[0],
-layer_1_w9[1],
-layer_1_w9[2],
-layer_2_w9[1],
-layer_2_w10[0]
-);
-compressor42 layer_2_compressor42_0(
-layer_1_w10[0],
-layer_1_w10[1],
-layer_1_w10[2],
-layer_1_w10[3],
-layer_1_w10[4],
-layer_2_w10[1],
-layer_2_w11[0],
-layer_2_w11[1]
-);
-full_adder layer_2_full_adder_3(
-layer_1_w11[0],
-layer_1_w11[1],
-layer_1_w11[2],
-layer_2_w11[2],
-layer_2_w12[0]
-);
-assign layer_2_w11[3]=layer_1_w11[3];
-full_adder layer_2_full_adder_4(
-layer_1_w12[0],
-layer_1_w12[1],
-layer_1_w12[2],
-layer_2_w12[1],
-layer_2_w13[0]
-);
-assign layer_2_w12[2]=layer_1_w12[3];
-compressor42 layer_2_compressor42_1(
-layer_1_w13[0],
-layer_1_w13[1],
-layer_1_w13[2],
-layer_1_w13[3],
-layer_1_w13[4],
-layer_2_w13[1],
-layer_2_w14[0],
-layer_2_w14[1]
-);
-assign layer_2_w13[2]=layer_1_w13[5];
-compressor42 layer_2_compressor42_2(
-layer_1_w14[0],
-layer_1_w14[1],
-layer_1_w14[2],
-layer_1_w14[3],
-layer_1_w14[4],
-layer_2_w14[2],
-layer_2_w15[0],
-layer_2_w15[1]
-);
-compressor42 layer_2_compressor42_3(
-layer_1_w15[0],
-layer_1_w15[1],
-layer_1_w15[2],
-layer_1_w15[3],
-layer_1_w15[4],
-layer_2_w15[2],
-layer_2_w16[0],
-layer_2_w16[1]
-);
-compressor42 layer_2_compressor42_4(
-layer_1_w16[0],
-layer_1_w16[1],
-layer_1_w16[2],
-layer_1_w16[3],
-layer_1_w16[4],
-layer_2_w16[2],
-layer_2_w17[0],
-layer_2_w17[1]
-);
-assign layer_2_w16[3]=layer_1_w16[5];
-compressor42 layer_2_compressor42_5(
-layer_1_w17[0],
-layer_1_w17[1],
-layer_1_w17[2],
-layer_1_w17[3],
-layer_1_w17[4],
-layer_2_w17[2],
-layer_2_w18[0],
-layer_2_w18[1]
-);
-compressor42 layer_2_compressor42_6(
-layer_1_w18[0],
-layer_1_w18[1],
-layer_1_w18[2],
-layer_1_w18[3],
-layer_1_w18[4],
-layer_2_w18[2],
-layer_2_w19[0],
-layer_2_w19[1]
-);
-assign layer_2_w18[3]=layer_1_w18[5];
-compressor42 layer_2_compressor42_7(
-layer_1_w19[0],
-layer_1_w19[1],
-layer_1_w19[2],
-layer_1_w19[3],
-layer_1_w19[4],
-layer_2_w19[2],
-layer_2_w20[0],
-layer_2_w20[1]
-);
-full_adder layer_2_full_adder_5(
-layer_1_w20[0],
-layer_1_w20[1],
-layer_1_w20[2],
-layer_2_w20[2],
-layer_2_w21[0]
-);
-assign layer_2_w20[3]=layer_1_w20[3];
-full_adder layer_2_full_adder_6(
-layer_1_w21[0],
-layer_1_w21[1],
-layer_1_w21[2],
-layer_2_w21[1],
-layer_2_w22[0]
-);
-assign layer_2_w21[2]=layer_1_w21[3];
-full_adder layer_2_full_adder_7(
-layer_1_w22[0],
-layer_1_w22[1],
-layer_1_w22[2],
-layer_2_w22[1],
-layer_2_w23[0]
-);
-full_adder layer_2_full_adder_8(
-layer_1_w23[0],
-layer_1_w23[1],
-layer_1_w23[2],
-layer_2_w23[1],
-layer_2_w24[0]
-);
-full_adder layer_2_full_adder_9(
-layer_1_w24[0],
-layer_1_w24[1],
-layer_1_w24[2],
-layer_2_w24[1],
-layer_2_w25[0]
-);
-assign layer_2_w24[2]=layer_1_w24[3];
-full_adder layer_2_full_adder_10(
-layer_1_w25[0],
-layer_1_w25[1],
-layer_1_w25[2],
-layer_2_w25[1],
-layer_2_w26[0]
-);
-assign layer_2_w26[1]=layer_1_w26[0];
-assign layer_2_w26[2]=layer_1_w26[1];
-assign layer_2_w27[0]=layer_1_w27[0];
-assign layer_2_w27[1]=layer_1_w27[1];
-full_adder layer_2_full_adder_11(
-layer_1_w28[0],
-layer_1_w28[1],
-layer_1_w28[2],
-layer_2_w28,
-layer_2_w29[0]
-);
-assign layer_2_w29[1]=layer_1_w29[0];
-assign layer_2_w29[2]=layer_1_w29[1];
-assign layer_2_w30=layer_1_w30;
-assign layer_2_w31=layer_1_w31;
-
-
-///////////////////////////////////////////////////////stage 1///////////////////////////////////////////////////////
-reg [1:0]reg_layer_2_w0;
-reg reg_layer_2_w1;
-reg [2:0]reg_layer_2_w2;
-reg [1:0]reg_layer_2_w3;
-reg [1:0]reg_layer_2_w4;
-reg [1:0]reg_layer_2_w5;
-reg [1:0]reg_layer_2_w6;
-reg [1:0]reg_layer_2_w7;
-reg [1:0]reg_layer_2_w8;
-reg [1:0]reg_layer_2_w9;
-reg [1:0]reg_layer_2_w10;
-reg [3:0]reg_layer_2_w11;
-reg [2:0]reg_layer_2_w12;
-reg [2:0]reg_layer_2_w13;
-reg [2:0]reg_layer_2_w14;
-reg [2:0]reg_layer_2_w15;
-reg [3:0]reg_layer_2_w16;
-reg [2:0]reg_layer_2_w17;
-reg [3:0]reg_layer_2_w18;
-reg [2:0]reg_layer_2_w19;
-reg [3:0]reg_layer_2_w20;
-reg [2:0]reg_layer_2_w21;
-reg [1:0]reg_layer_2_w22;
-reg [1:0]reg_layer_2_w23;
-reg [2:0]reg_layer_2_w24;
-reg [1:0]reg_layer_2_w25;
-reg [2:0]reg_layer_2_w26;
-reg [1:0]reg_layer_2_w27;
-reg reg_layer_2_w28;
-reg [2:0]reg_layer_2_w29;
-reg reg_layer_2_w30;
-reg reg_layer_2_w31;
-reg stage_1_ready;
-assign o_ready=stage_1_ready;
-
-always @(posedge i_clk or negedge i_rst)begin
- if(!i_rst)begin
- stage_1_ready<=0;
- reg_layer_2_w0<=0;
- reg_layer_2_w1<=0;
- reg_layer_2_w2<=0;
- reg_layer_2_w3<=0;
- reg_layer_2_w4<=0;
- reg_layer_2_w5<=0;
- reg_layer_2_w6<=0;
- reg_layer_2_w7<=0;
- reg_layer_2_w8<=0;
- reg_layer_2_w9<=0;
- reg_layer_2_w10<=0;
- reg_layer_2_w11<=0;
- reg_layer_2_w12<=0;
- reg_layer_2_w13<=0;
- reg_layer_2_w14<=0;
- reg_layer_2_w15<=0;
- reg_layer_2_w16<=0;
- reg_layer_2_w17<=0;
- reg_layer_2_w18<=0;
- reg_layer_2_w19<=0;
- reg_layer_2_w20<=0;
- reg_layer_2_w21<=0;
- reg_layer_2_w22<=0;
- reg_layer_2_w23<=0;
- reg_layer_2_w24<=0;
- reg_layer_2_w25<=0;
- reg_layer_2_w26<=0;
- reg_layer_2_w27<=0;
- reg_layer_2_w28<=0;
- reg_layer_2_w29<=0;
- reg_layer_2_w30<=0;
- reg_layer_2_w31<=0;
- end
- else begin
- if(stage_0_ready)begin
- reg_layer_2_w0<=layer_2_w0;
- reg_layer_2_w1<=layer_2_w1;
- reg_layer_2_w2<=layer_2_w2;
- reg_layer_2_w3<=layer_2_w3;
- reg_layer_2_w4<=layer_2_w4;
- reg_layer_2_w5<=layer_2_w5;
- reg_layer_2_w6<=layer_2_w6;
- reg_layer_2_w7<=layer_2_w7;
- reg_layer_2_w8<=layer_2_w8;
- reg_layer_2_w9<=layer_2_w9;
- reg_layer_2_w10<=layer_2_w10;
- reg_layer_2_w11<=layer_2_w11;
- reg_layer_2_w12<=layer_2_w12;
- reg_layer_2_w13<=layer_2_w13;
- reg_layer_2_w14<=layer_2_w14;
- reg_layer_2_w15<=layer_2_w15;
- reg_layer_2_w16<=layer_2_w16;
- reg_layer_2_w17<=layer_2_w17;
- reg_layer_2_w18<=layer_2_w18;
- reg_layer_2_w19<=layer_2_w19;
- reg_layer_2_w20<=layer_2_w20;
- reg_layer_2_w21<=layer_2_w21;
- reg_layer_2_w22<=layer_2_w22;
- reg_layer_2_w23<=layer_2_w23;
- reg_layer_2_w24<=layer_2_w24;
- reg_layer_2_w25<=layer_2_w25;
- reg_layer_2_w26<=layer_2_w26;
- reg_layer_2_w27<=layer_2_w27;
- reg_layer_2_w28<=layer_2_w28;
- reg_layer_2_w29<=layer_2_w29;
- reg_layer_2_w30<=layer_2_w30;
- reg_layer_2_w31<=layer_2_w31;
- end
- stage_1_ready<=stage_0_ready;
- end
-end
-
-//layer 3
-wire layer_3_w0[1:0];
-wire layer_3_w1;
-wire layer_3_w2[2:0];
-wire layer_3_w3[1:0];
-wire layer_3_w4[1:0];
-wire layer_3_w5[1:0];
-wire layer_3_w6[1:0];
-wire layer_3_w7[1:0];
-wire layer_3_w8[1:0];
-wire layer_3_w9[1:0];
-wire layer_3_w10[1:0];
-wire layer_3_w11[1:0];
-wire layer_3_w12[1:0];
-wire layer_3_w13[1:0];
-wire layer_3_w14[1:0];
-wire layer_3_w15[1:0];
-wire layer_3_w16[2:0];
-wire layer_3_w17[1:0];
-wire layer_3_w18[2:0];
-wire layer_3_w19[1:0];
-wire layer_3_w20[2:0];
-wire layer_3_w21[1:0];
-wire layer_3_w22[2:0];
-wire layer_3_w23[1:0];
-wire layer_3_w24;
-wire layer_3_w25[2:0];
-wire layer_3_w26;
-wire layer_3_w27[2:0];
-wire layer_3_w28;
-wire layer_3_w29;
-wire layer_3_w30[1:0];
-wire layer_3_w31;
-assign layer_3_w0[0]=reg_layer_2_w0[0];
-assign layer_3_w0[1]=reg_layer_2_w0[1];
-assign layer_3_w1=reg_layer_2_w1;
-assign layer_3_w2[0]=reg_layer_2_w2[0];
-assign layer_3_w2[1]=reg_layer_2_w2[1];
-assign layer_3_w2[2]=reg_layer_2_w2[2];
-assign layer_3_w3[0]=reg_layer_2_w3[0];
-assign layer_3_w3[1]=reg_layer_2_w3[1];
-assign layer_3_w4[0]=reg_layer_2_w4[0];
-assign layer_3_w4[1]=reg_layer_2_w4[1];
-assign layer_3_w5[0]=reg_layer_2_w5[0];
-assign layer_3_w5[1]=reg_layer_2_w5[1];
-assign layer_3_w6[0]=reg_layer_2_w6[0];
-assign layer_3_w6[1]=reg_layer_2_w6[1];
-assign layer_3_w7[0]=reg_layer_2_w7[0];
-assign layer_3_w7[1]=reg_layer_2_w7[1];
-assign layer_3_w8[0]=reg_layer_2_w8[0];
-assign layer_3_w8[1]=reg_layer_2_w8[1];
-assign layer_3_w9[0]=reg_layer_2_w9[0];
-assign layer_3_w9[1]=reg_layer_2_w9[1];
-assign layer_3_w10[0]=reg_layer_2_w10[0];
-assign layer_3_w10[1]=reg_layer_2_w10[1];
-full_adder layer_3_full_adder_0(
-reg_layer_2_w11[0],
-reg_layer_2_w11[1],
-reg_layer_2_w11[2],
-layer_3_w11[0],
-layer_3_w12[0]
-);
-assign layer_3_w11[1]=reg_layer_2_w11[3];
-full_adder layer_3_full_adder_1(
-reg_layer_2_w12[0],
-reg_layer_2_w12[1],
-reg_layer_2_w12[2],
-layer_3_w12[1],
-layer_3_w13[0]
-);
-full_adder layer_3_full_adder_2(
-reg_layer_2_w13[0],
-reg_layer_2_w13[1],
-reg_layer_2_w13[2],
-layer_3_w13[1],
-layer_3_w14[0]
-);
-full_adder layer_3_full_adder_3(
-reg_layer_2_w14[0],
-reg_layer_2_w14[1],
-reg_layer_2_w14[2],
-layer_3_w14[1],
-layer_3_w15[0]
-);
-full_adder layer_3_full_adder_4(
-reg_layer_2_w15[0],
-reg_layer_2_w15[1],
-reg_layer_2_w15[2],
-layer_3_w15[1],
-layer_3_w16[0]
-);
-full_adder layer_3_full_adder_5(
-reg_layer_2_w16[0],
-reg_layer_2_w16[1],
-reg_layer_2_w16[2],
-layer_3_w16[1],
-layer_3_w17[0]
-);
-assign layer_3_w16[2]=reg_layer_2_w16[3];
-full_adder layer_3_full_adder_6(
-reg_layer_2_w17[0],
-reg_layer_2_w17[1],
-reg_layer_2_w17[2],
-layer_3_w17[1],
-layer_3_w18[0]
-);
-full_adder layer_3_full_adder_7(
-reg_layer_2_w18[0],
-reg_layer_2_w18[1],
-reg_layer_2_w18[2],
-layer_3_w18[1],
-layer_3_w19[0]
-);
-assign layer_3_w18[2]=reg_layer_2_w18[3];
-full_adder layer_3_full_adder_8(
-reg_layer_2_w19[0],
-reg_layer_2_w19[1],
-reg_layer_2_w19[2],
-layer_3_w19[1],
-layer_3_w20[0]
-);
-full_adder layer_3_full_adder_9(
-reg_layer_2_w20[0],
-reg_layer_2_w20[1],
-reg_layer_2_w20[2],
-layer_3_w20[1],
-layer_3_w21[0]
-);
-assign layer_3_w20[2]=reg_layer_2_w20[3];
-full_adder layer_3_full_adder_10(
-reg_layer_2_w21[0],
-reg_layer_2_w21[1],
-reg_layer_2_w21[2],
-layer_3_w21[1],
-layer_3_w22[0]
-);
-assign layer_3_w22[1]=reg_layer_2_w22[0];
-assign layer_3_w22[2]=reg_layer_2_w22[1];
-assign layer_3_w23[0]=reg_layer_2_w23[0];
-assign layer_3_w23[1]=reg_layer_2_w23[1];
-full_adder layer_3_full_adder_11(
-reg_layer_2_w24[0],
-reg_layer_2_w24[1],
-reg_layer_2_w24[2],
-layer_3_w24,
-layer_3_w25[0]
-);
-assign layer_3_w25[1]=reg_layer_2_w25[0];
-assign layer_3_w25[2]=reg_layer_2_w25[1];
-full_adder layer_3_full_adder_12(
-reg_layer_2_w26[0],
-reg_layer_2_w26[1],
-reg_layer_2_w26[2],
-layer_3_w26,
-layer_3_w27[0]
-);
-assign layer_3_w27[1]=reg_layer_2_w27[0];
-assign layer_3_w27[2]=reg_layer_2_w27[1];
-assign layer_3_w28=reg_layer_2_w28;
-full_adder layer_3_full_adder_13(
-reg_layer_2_w29[0],
-reg_layer_2_w29[1],
-reg_layer_2_w29[2],
-layer_3_w29,
-layer_3_w30[0]
-);
-assign layer_3_w30[1]=reg_layer_2_w30;
-assign layer_3_w31=reg_layer_2_w31;
-
-//layer 4
-wire layer_4_w0[1:0];
-wire layer_4_w1;
-wire layer_4_w2;
-wire layer_4_w3[1:0];
-wire layer_4_w4[1:0];
-wire layer_4_w5[1:0];
-wire layer_4_w6[1:0];
-wire layer_4_w7[1:0];
-wire layer_4_w8[1:0];
-wire layer_4_w9[1:0];
-wire layer_4_w10[1:0];
-wire layer_4_w11[1:0];
-wire layer_4_w12[1:0];
-wire layer_4_w13[1:0];
-wire layer_4_w14[1:0];
-wire layer_4_w15[1:0];
-wire layer_4_w16[1:0];
-wire layer_4_w17[1:0];
-wire layer_4_w18[1:0];
-wire layer_4_w19[1:0];
-wire layer_4_w20[1:0];
-wire layer_4_w21[1:0];
-wire layer_4_w22[1:0];
-wire layer_4_w23[1:0];
-wire layer_4_w24[1:0];
-wire layer_4_w25;
-wire layer_4_w26[1:0];
-wire layer_4_w27;
-wire layer_4_w28[1:0];
-wire layer_4_w29;
-wire layer_4_w30[1:0];
-wire layer_4_w31;
-assign layer_4_w0[0]=layer_3_w0[0];
-assign layer_4_w0[1]=layer_3_w0[1];
-assign layer_4_w1=layer_3_w1;
-full_adder layer_4_full_adder_0(
-layer_3_w2[0],
-layer_3_w2[1],
-layer_3_w2[2],
-layer_4_w2,
-layer_4_w3[0]
-);
-half_adder layer_4_half_adder_0(
-layer_3_w3[0],
-layer_3_w3[1],
-layer_4_w3[1],
-layer_4_w4[0]
-);
-half_adder layer_4_half_adder_1(
-layer_3_w4[0],
-layer_3_w4[1],
-layer_4_w4[1],
-layer_4_w5[0]
-);
-half_adder layer_4_half_adder_2(
-layer_3_w5[0],
-layer_3_w5[1],
-layer_4_w5[1],
-layer_4_w6[0]
-);
-half_adder layer_4_half_adder_3(
-layer_3_w6[0],
-layer_3_w6[1],
-layer_4_w6[1],
-layer_4_w7[0]
-);
-half_adder layer_4_half_adder_4(
-layer_3_w7[0],
-layer_3_w7[1],
-layer_4_w7[1],
-layer_4_w8[0]
-);
-half_adder layer_4_half_adder_5(
-layer_3_w8[0],
-layer_3_w8[1],
-layer_4_w8[1],
-layer_4_w9[0]
-);
-half_adder layer_4_half_adder_6(
-layer_3_w9[0],
-layer_3_w9[1],
-layer_4_w9[1],
-layer_4_w10[0]
-);
-half_adder layer_4_half_adder_7(
-layer_3_w10[0],
-layer_3_w10[1],
-layer_4_w10[1],
-layer_4_w11[0]
-);
-half_adder layer_4_half_adder_8(
-layer_3_w11[0],
-layer_3_w11[1],
-layer_4_w11[1],
-layer_4_w12[0]
-);
-half_adder layer_4_half_adder_9(
-layer_3_w12[0],
-layer_3_w12[1],
-layer_4_w12[1],
-layer_4_w13[0]
-);
-half_adder layer_4_half_adder_10(
-layer_3_w13[0],
-layer_3_w13[1],
-layer_4_w13[1],
-layer_4_w14[0]
-);
-half_adder layer_4_half_adder_11(
-layer_3_w14[0],
-layer_3_w14[1],
-layer_4_w14[1],
-layer_4_w15[0]
-);
-half_adder layer_4_half_adder_12(
-layer_3_w15[0],
-layer_3_w15[1],
-layer_4_w15[1],
-layer_4_w16[0]
-);
-full_adder layer_4_full_adder_1(
-layer_3_w16[0],
-layer_3_w16[1],
-layer_3_w16[2],
-layer_4_w16[1],
-layer_4_w17[0]
-);
-half_adder layer_4_half_adder_13(
-layer_3_w17[0],
-layer_3_w17[1],
-layer_4_w17[1],
-layer_4_w18[0]
-);
-full_adder layer_4_full_adder_2(
-layer_3_w18[0],
-layer_3_w18[1],
-layer_3_w18[2],
-layer_4_w18[1],
-layer_4_w19[0]
-);
-half_adder layer_4_half_adder_14(
-layer_3_w19[0],
-layer_3_w19[1],
-layer_4_w19[1],
-layer_4_w20[0]
-);
-full_adder layer_4_full_adder_3(
-layer_3_w20[0],
-layer_3_w20[1],
-layer_3_w20[2],
-layer_4_w20[1],
-layer_4_w21[0]
-);
-half_adder layer_4_half_adder_15(
-layer_3_w21[0],
-layer_3_w21[1],
-layer_4_w21[1],
-layer_4_w22[0]
-);
-full_adder layer_4_full_adder_4(
-layer_3_w22[0],
-layer_3_w22[1],
-layer_3_w22[2],
-layer_4_w22[1],
-layer_4_w23[0]
-);
-half_adder layer_4_half_adder_16(
-layer_3_w23[0],
-layer_3_w23[1],
-layer_4_w23[1],
-layer_4_w24[0]
-);
-assign layer_4_w24[1]=layer_3_w24;
-full_adder layer_4_full_adder_5(
-layer_3_w25[0],
-layer_3_w25[1],
-layer_3_w25[2],
-layer_4_w25,
-layer_4_w26[0]
-);
-assign layer_4_w26[1]=layer_3_w26;
-full_adder layer_4_full_adder_6(
-layer_3_w27[0],
-layer_3_w27[1],
-layer_3_w27[2],
-layer_4_w27,
-layer_4_w28[0]
-);
-assign layer_4_w28[1]=layer_3_w28;
-assign layer_4_w29=layer_3_w29;
-assign layer_4_w30[0]=layer_3_w30[0];
-assign layer_4_w30[1]=layer_3_w30[1];
-assign layer_4_w31=layer_3_w31;
-
-//group reduction results into 2 numbers
-wire [31:0]A,B;
-assign A[0]=layer_4_w0[0];
-assign B[0]=layer_4_w0[1];
-assign A[1]=layer_4_w1;
-assign B[1]=0;
-assign A[2]=layer_4_w2;
-assign B[2]=0;
-assign A[3]=layer_4_w3[0];
-assign B[3]=layer_4_w3[1];
-assign A[4]=layer_4_w4[0];
-assign B[4]=layer_4_w4[1];
-assign A[5]=layer_4_w5[0];
-assign B[5]=layer_4_w5[1];
-assign A[6]=layer_4_w6[0];
-assign B[6]=layer_4_w6[1];
-assign A[7]=layer_4_w7[0];
-assign B[7]=layer_4_w7[1];
-assign A[8]=layer_4_w8[0];
-assign B[8]=layer_4_w8[1];
-assign A[9]=layer_4_w9[0];
-assign B[9]=layer_4_w9[1];
-assign A[10]=layer_4_w10[0];
-assign B[10]=layer_4_w10[1];
-assign A[11]=layer_4_w11[0];
-assign B[11]=layer_4_w11[1];
-assign A[12]=layer_4_w12[0];
-assign B[12]=layer_4_w12[1];
-assign A[13]=layer_4_w13[0];
-assign B[13]=layer_4_w13[1];
-assign A[14]=layer_4_w14[0];
-assign B[14]=layer_4_w14[1];
-assign A[15]=layer_4_w15[0];
-assign B[15]=layer_4_w15[1];
-assign A[16]=layer_4_w16[0];
-assign B[16]=layer_4_w16[1];
-assign A[17]=layer_4_w17[0];
-assign B[17]=layer_4_w17[1];
-assign A[18]=layer_4_w18[0];
-assign B[18]=layer_4_w18[1];
-assign A[19]=layer_4_w19[0];
-assign B[19]=layer_4_w19[1];
-assign A[20]=layer_4_w20[0];
-assign B[20]=layer_4_w20[1];
-assign A[21]=layer_4_w21[0];
-assign B[21]=layer_4_w21[1];
-assign A[22]=layer_4_w22[0];
-assign B[22]=layer_4_w22[1];
-assign A[23]=layer_4_w23[0];
-assign B[23]=layer_4_w23[1];
-assign A[24]=layer_4_w24[0];
-assign B[24]=layer_4_w24[1];
-assign A[25]=layer_4_w25;
-assign B[25]=0;
-assign A[26]=layer_4_w26[0];
-assign B[26]=layer_4_w26[1];
-assign A[27]=layer_4_w27;
-assign B[27]=0;
-assign A[28]=layer_4_w28[0];
-assign B[28]=layer_4_w28[1];
-assign A[29]=layer_4_w29;
-assign B[29]=0;
-assign A[30]=layer_4_w30[0];
-assign B[30]=layer_4_w30[1];
-assign A[31]=layer_4_w31;
-assign B[31]=0;
-
-wire carry;
-adder_32bit adder_32bit(
-A,
-B,
-1'b0,
-o_product,
-carry
-);
-
-
-endmodule
diff --git a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/CLA_fixed.v b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/CLA_fixed.v
deleted file mode 100644
index bd68e0204..000000000
--- a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/CLA_fixed.v
+++ /dev/null
@@ -1,259 +0,0 @@
-/*Carry look-ahead adder
-Author: Zhu Xu
-Email: m99a1@yahoo.cn
-*/
-
-module operator_A(
-input A,
-input B,
-output P,
-output G
-);
-
-assign P=A^B;
-assign G=A&B;
-
-endmodule
-
-module operator_B(
-input P,G,P1,G1,
-output Po,Go
-);
-
-assign Po=P&P1;
-assign Go=G|(P&G1);
-
-endmodule
-
-module operator_C(
-input P,G,G1,
-output Go
-);
-
-assign Go=G|(P&G1);
-
-endmodule
-
-
-/* 32-bit prefix-2 Han-Carlson adder
-stage 0: Number of Generation=32, NP=32, NOA=32, NOB=0, NOC=0.
-stage 1: NG=16, NP=15, NOA=0, NOB=15, NOC=1.
-stage 2: NG=16, NP=14, NOA=0, NOB=14, NOC=1.
-stage 3: NG=16, NP=12, NOA=0, NOB=12, NOC=2.
-stage 4: NG=16, NP=8, NOA=0, NOB=8, NOC=4.
-stage 5: NG=16, NP=0, NOA=0, NOB=0, NOC=8.
-stage 6; NG=32, NP=0, NOA=0, NOB=0, NOC=15.
-*/
-module adder_32bit(
-input [31:0]i_a,i_b,
-input i_c,
-output [31:0]o_s,
-output o_c
-);
-
-//stage 0
-wire [31:0]P0,G0;
-operator_A operator_A_0(i_a[0],i_b[0],P0[0],G0[0]);
-operator_A operator_A_1(i_a[1],i_b[1],P0[1],G0[1]);
-operator_A operator_A_2(i_a[2],i_b[2],P0[2],G0[2]);
-operator_A operator_A_3(i_a[3],i_b[3],P0[3],G0[3]);
-operator_A operator_A_4(i_a[4],i_b[4],P0[4],G0[4]);
-operator_A operator_A_5(i_a[5],i_b[5],P0[5],G0[5]);
-operator_A operator_A_6(i_a[6],i_b[6],P0[6],G0[6]);
-operator_A operator_A_7(i_a[7],i_b[7],P0[7],G0[7]);
-operator_A operator_A_8(i_a[8],i_b[8],P0[8],G0[8]);
-operator_A operator_A_9(i_a[9],i_b[9],P0[9],G0[9]);
-operator_A operator_A_10(i_a[10],i_b[10],P0[10],G0[10]);
-operator_A operator_A_11(i_a[11],i_b[11],P0[11],G0[11]);
-operator_A operator_A_12(i_a[12],i_b[12],P0[12],G0[12]);
-operator_A operator_A_13(i_a[13],i_b[13],P0[13],G0[13]);
-operator_A operator_A_14(i_a[14],i_b[14],P0[14],G0[14]);
-operator_A operator_A_15(i_a[15],i_b[15],P0[15],G0[15]);
-operator_A operator_A_16(i_a[16],i_b[16],P0[16],G0[16]);
-operator_A operator_A_17(i_a[17],i_b[17],P0[17],G0[17]);
-operator_A operator_A_18(i_a[18],i_b[18],P0[18],G0[18]);
-operator_A operator_A_19(i_a[19],i_b[19],P0[19],G0[19]);
-operator_A operator_A_20(i_a[20],i_b[20],P0[20],G0[20]);
-operator_A operator_A_21(i_a[21],i_b[21],P0[21],G0[21]);
-operator_A operator_A_22(i_a[22],i_b[22],P0[22],G0[22]);
-operator_A operator_A_23(i_a[23],i_b[23],P0[23],G0[23]);
-operator_A operator_A_24(i_a[24],i_b[24],P0[24],G0[24]);
-operator_A operator_A_25(i_a[25],i_b[25],P0[25],G0[25]);
-operator_A operator_A_26(i_a[26],i_b[26],P0[26],G0[26]);
-operator_A operator_A_27(i_a[27],i_b[27],P0[27],G0[27]);
-operator_A operator_A_28(i_a[28],i_b[28],P0[28],G0[28]);
-operator_A operator_A_29(i_a[29],i_b[29],P0[29],G0[29]);
-operator_A operator_A_30(i_a[30],i_b[30],P0[30],G0[30]);
-operator_A operator_A_31(i_a[31],i_b[31],P0[31],G0[31]);
-
-//stage 1
-wire [15:0]G1;
-wire [15:1]P1;
-operator_C operator_C_stage_1_0(P0[0],G0[0],i_c,G1[0]);
-operator_B operator_B_stage_1_1(P0[2],G0[2],P0[1],G0[1],P1[1],G1[1]);
-operator_B operator_B_stage_1_2(P0[4],G0[4],P0[3],G0[3],P1[2],G1[2]);
-operator_B operator_B_stage_1_3(P0[6],G0[6],P0[5],G0[5],P1[3],G1[3]);
-operator_B operator_B_stage_1_4(P0[8],G0[8],P0[7],G0[7],P1[4],G1[4]);
-operator_B operator_B_stage_1_5(P0[10],G0[10],P0[9],G0[9],P1[5],G1[5]);
-operator_B operator_B_stage_1_6(P0[12],G0[12],P0[11],G0[11],P1[6],G1[6]);
-operator_B operator_B_stage_1_7(P0[14],G0[14],P0[13],G0[13],P1[7],G1[7]);
-operator_B operator_B_stage_1_8(P0[16],G0[16],P0[15],G0[15],P1[8],G1[8]);
-operator_B operator_B_stage_1_9(P0[18],G0[18],P0[17],G0[17],P1[9],G1[9]);
-operator_B operator_B_stage_1_10(P0[20],G0[20],P0[19],G0[19],P1[10],G1[10]);
-operator_B operator_B_stage_1_11(P0[22],G0[22],P0[21],G0[21],P1[11],G1[11]);
-operator_B operator_B_stage_1_12(P0[24],G0[24],P0[23],G0[23],P1[12],G1[12]);
-operator_B operator_B_stage_1_13(P0[26],G0[26],P0[25],G0[25],P1[13],G1[13]);
-operator_B operator_B_stage_1_14(P0[28],G0[28],P0[27],G0[27],P1[14],G1[14]);
-operator_B operator_B_stage_1_15(P0[30],G0[30],P0[29],G0[29],P1[15],G1[15]);
-
-
-
-//stage 2
-wire [15:0]G2;
-wire [15:2]P2;
-assign G2[0]=G1[0];
-operator_C operator_C_stage_2_1(P1[1],G1[1],G1[0],G2[1]);
-operator_B operator_B_stage_2_2(P1[2], G1[2],P1[1],G1[1],P2[2],G2[2]);
-operator_B operator_B_stage_2_3(P1[3], G1[3],P1[2],G1[2],P2[3],G2[3]);
-operator_B operator_B_stage_2_4(P1[4], G1[4],P1[3],G1[3],P2[4],G2[4]);
-operator_B operator_B_stage_2_5(P1[5], G1[5],P1[4],G1[4],P2[5],G2[5]);
-operator_B operator_B_stage_2_6(P1[6], G1[6],P1[5],G1[5],P2[6],G2[6]);
-operator_B operator_B_stage_2_7(P1[7], G1[7],P1[6],G1[6],P2[7],G2[7]);
-operator_B operator_B_stage_2_8(P1[8], G1[8],P1[7],G1[7],P2[8],G2[8]);
-operator_B operator_B_stage_2_9(P1[9], G1[9],P1[8],G1[8],P2[9],G2[9]);
-operator_B operator_B_stage_2_10(P1[10], G1[10],P1[9],G1[9],P2[10],G2[10]);
-operator_B operator_B_stage_2_11(P1[11], G1[11],P1[10],G1[10],P2[11],G2[11]);
-operator_B operator_B_stage_2_12(P1[12], G1[12],P1[11],G1[11],P2[12],G2[12]);
-operator_B operator_B_stage_2_13(P1[13], G1[13],P1[12],G1[12],P2[13],G2[13]);
-operator_B operator_B_stage_2_14(P1[14], G1[14],P1[13],G1[13],P2[14],G2[14]);
-operator_B operator_B_stage_2_15(P1[15], G1[15],P1[14],G1[14],P2[15],G2[15]);
-
-//stage 3
-wire [15:0]G3;
-wire [15:4]P3;
-assign G3[0]=G2[0];
-assign G3[1]=G2[1];
-operator_C operator_C_stage_3_2(P2[2],G2[2],G2[0],G3[2]);
-operator_C operator_C_stage_3_3(P2[3],G2[3],G2[1],G3[3]);
-operator_B operator_B_stage_3_4(P2[4], G2[4],P2[2],G2[2],P3[4],G3[4]);
-operator_B operator_B_stage_3_5(P2[5], G2[5],P2[3],G2[3],P3[5],G3[5]);
-operator_B operator_B_stage_3_6(P2[6], G2[6],P2[4],G2[4],P3[6],G3[6]);
-operator_B operator_B_stage_3_7(P2[7], G2[7],P2[5],G2[5],P3[7],G3[7]);
-operator_B operator_B_stage_3_8(P2[8], G2[8],P2[6],G2[6],P3[8],G3[8]);
-operator_B operator_B_stage_3_9(P2[9], G2[9],P2[7],G2[7],P3[9],G3[9]);
-operator_B operator_B_stage_3_10(P2[10], G2[10],P2[8],G2[8],P3[10],G3[10]);
-operator_B operator_B_stage_3_11(P2[11], G2[11],P2[9],G2[9],P3[11],G3[11]);
-operator_B operator_B_stage_3_12(P2[12], G2[12],P2[10],G2[10],P3[12],G3[12]);
-operator_B operator_B_stage_3_13(P2[13], G2[13],P2[11],G2[11],P3[13],G3[13]);
-operator_B operator_B_stage_3_14(P2[14], G2[14],P2[12],G2[12],P3[14],G3[14]);
-operator_B operator_B_stage_3_15(P2[15], G2[15],P2[13],G2[13],P3[15],G3[15]);
-
-//stage 4
-wire [15:0]G4;
-wire [15:8]P4;
-assign G4[0]=G3[0];
-assign G4[1]=G3[1];
-assign G4[2]=G3[2];
-assign G4[3]=G3[3];
-operator_C operator_C_stage_4_4(P3[4],G3[4],G3[0],G4[4]);
-operator_C operator_C_stage_4_5(P3[5],G3[5],G3[1],G4[5]);
-operator_C operator_C_stage_4_6(P3[6],G3[6],G3[2],G4[6]);
-operator_C operator_C_stage_4_7(P3[7],G3[7],G3[3],G4[7]);
-operator_B operator_B_stage_4_8(P3[8], G3[8],P3[4],G3[4],P4[8],G4[8]);
-operator_B operator_B_stage_4_9(P3[9], G3[9],P3[5],G3[5],P4[9],G4[9]);
-operator_B operator_B_stage_4_10(P3[10], G3[10],P3[6],G3[6],P4[10],G4[10]);
-operator_B operator_B_stage_4_11(P3[11], G3[11],P3[7],G3[7],P4[11],G4[11]);
-operator_B operator_B_stage_4_12(P3[12], G3[12],P3[8],G3[8],P4[12],G4[12]);
-operator_B operator_B_stage_4_13(P3[13], G3[13],P3[9],G3[9],P4[13],G4[13]);
-operator_B operator_B_stage_4_14(P3[14], G3[14],P3[10],G3[10],P4[14],G4[14]);
-operator_B operator_B_stage_4_15(P3[15], G3[15],P3[11],G3[11],P4[15],G4[15]);
-
-//stage 5
-wire [15:0]G5;
-assign G5[0]=G4[0];
-assign G5[1]=G4[1];
-assign G5[2]=G4[2];
-assign G5[3]=G4[3];
-assign G5[4]=G4[4];
-assign G5[5]=G4[5];
-assign G5[6]=G4[6];
-assign G5[7]=G4[7];
-operator_C operator_C_stage_5_8(P4[8],G4[8],G4[0],G5[8]);
-operator_C operator_C_stage_5_9(P4[9],G4[9],G4[1],G5[9]);
-operator_C operator_C_stage_5_10(P4[10],G4[10],G4[2],G5[10]);
-operator_C operator_C_stage_5_11(P4[11],G4[11],G4[3],G5[11]);
-operator_C operator_C_stage_5_12(P4[12],G4[12],G4[4],G5[12]);
-operator_C operator_C_stage_5_13(P4[13],G4[13],G4[5],G5[13]);
-operator_C operator_C_stage_5_14(P4[14],G4[14],G4[6],G5[14]);
-operator_C operator_C_stage_5_15(P4[15],G4[15],G4[7],G5[15]);
-
-//stage 6
-wire [31:0]G6;
-assign G6[0]=G5[0];
-assign G6[2]=G5[1];
-assign G6[4]=G5[2];
-assign G6[6]=G5[3];
-assign G6[8]=G5[4];
-assign G6[10]=G5[5];
-assign G6[12]=G5[6];
-assign G6[14]=G5[7];
-assign G6[16]=G5[8];
-assign G6[18]=G5[9];
-assign G6[20]=G5[10];
-assign G6[22]=G5[11];
-assign G6[24]=G5[12];
-assign G6[26]=G5[13];
-assign G6[28]=G5[14];
-assign G6[30]=G5[15];
-operator_C operator_C_stage_6_0(P0[1],G0[1],G5[0],G6[1]);
-operator_C operator_C_stage_6_1(P0[3],G0[3],G5[1],G6[3]);
-operator_C operator_C_stage_6_2(P0[5],G0[5],G5[2],G6[5]);
-operator_C operator_C_stage_6_3(P0[7],G0[7],G5[3],G6[7]);
-operator_C operator_C_stage_6_4(P0[9],G0[9],G5[4],G6[9]);
-operator_C operator_C_stage_6_5(P0[11],G0[11],G5[5],G6[11]);
-operator_C operator_C_stage_6_6(P0[13],G0[13],G5[6],G6[13]);
-operator_C operator_C_stage_6_7(P0[15],G0[15],G5[7],G6[15]);
-operator_C operator_C_stage_6_8(P0[17],G0[17],G5[8],G6[17]);
-operator_C operator_C_stage_6_9(P0[19],G0[19],G5[9],G6[19]);
-operator_C operator_C_stage_6_10(P0[21],G0[21],G5[10],G6[21]);
-operator_C operator_C_stage_6_11(P0[23],G0[23],G5[11],G6[23]);
-operator_C operator_C_stage_6_12(P0[25],G0[25],G5[12],G6[25]);
-operator_C operator_C_stage_6_13(P0[27],G0[27],G5[13],G6[27]);
-operator_C operator_C_stage_6_14(P0[29],G0[29],G5[14],G6[29]);
-operator_C operator_C_stage_6_15(P0[31],G0[31],G5[15],G6[31]);
-
-assign o_s[0]=P0[0]^i_c;
-assign o_s[1]=P0[1]^G6[0];
-assign o_s[2]=P0[2]^G6[1];
-assign o_s[3]=P0[3]^G6[2];
-assign o_s[4]=P0[4]^G6[3];
-assign o_s[5]=P0[5]^G6[4];
-assign o_s[6]=P0[6]^G6[5];
-assign o_s[7]=P0[7]^G6[6];
-assign o_s[8]=P0[8]^G6[7];
-assign o_s[9]=P0[9]^G6[8];
-assign o_s[10]=P0[10]^G6[9];
-assign o_s[11]=P0[11]^G6[10];
-assign o_s[12]=P0[12]^G6[11];
-assign o_s[13]=P0[13]^G6[12];
-assign o_s[14]=P0[14]^G6[13];
-assign o_s[15]=P0[15]^G6[14];
-assign o_s[16]=P0[16]^G6[15];
-assign o_s[17]=P0[17]^G6[16];
-assign o_s[18]=P0[18]^G6[17];
-assign o_s[19]=P0[19]^G6[18];
-assign o_s[20]=P0[20]^G6[19];
-assign o_s[21]=P0[21]^G6[20];
-assign o_s[22]=P0[22]^G6[21];
-assign o_s[23]=P0[23]^G6[22];
-assign o_s[24]=P0[24]^G6[23];
-assign o_s[25]=P0[25]^G6[24];
-assign o_s[26]=P0[26]^G6[25];
-assign o_s[27]=P0[27]^G6[26];
-assign o_s[28]=P0[28]^G6[27];
-assign o_s[29]=P0[29]^G6[28];
-assign o_s[30]=P0[30]^G6[29];
-assign o_s[31]=P0[31]^G6[30];
-assign o_c=G6[31];
-
-endmodule
\ No newline at end of file
diff --git a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/PID.v b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/PID.v
deleted file mode 100644
index 086156ddd..000000000
--- a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/PID.v
+++ /dev/null
@@ -1,434 +0,0 @@
-/* PID controller
-
-sigma=Ki*e(n)+sigma
-u(n)=(Kp+Kd)*e(n)+sigma+Kd*(-e(n-1))
-
-Data width of Wishbone slave port can be can be toggled between 64-bit, 32-bit and 16-bit.
-Address width of Wishbone slave port can be can be modified by changing parameter adr_wb_nb.
-
-Wishbone compliant
-Work as Wishbone slave, support Classic standard SINGLE/BLOCK READ/WRITE Cycle
-
-registers or wires
-[15:0]kp,ki,kd,sp,pv; can be both read and written
-[15:0]kpd; read only
-[15:0]err[0:1]; read only
-[15:0]mr,md; not accessable
-[31:0]p,b; not accessable
-[31:0]un,sigma; read only
-RS write 0 to RS will reset err[0], OF, un and sigma
-
-
-
-[4:0]of; overflow register, read only through Wishbone interface, address: 0x40
-of[0]==1 : kpd overflow
-of[1]==1 : err[0] overflow
-of[2]==1 : err[1] overflow
-of[3]==1 : un overflow
-of[4]==1 : sigma overflow
-[0:15]rl; read lock, when asserted corelated reagister can not be read through Wishbone interface
-[0:7]wl; write lock, when asserted corelated reagister can not be written through Wishbone interface
-
-
-
-*/
-
-`include "PID_defines.v"
-
-module PID #(
-`ifdef wb_16bit
-parameter wb_nb=16,
-`endif
-`ifdef wb_32bit
-parameter wb_nb=32,
-`endif
-`ifdef wb_64bit
-parameter wb_nb=64,
-`endif
- adr_wb_nb=16,
- kp_adr = 0,
- ki_adr = 1,
- kd_adr = 2,
- sp_adr = 3,
- pv_adr = 4,
- kpd_adr = 5,
- err_0_adr = 6,
- err_1_adr = 7,
- un_adr = 8,
- sigma_adr = 9,
- of_adr = 10,
- RS_adr = 11
-)(
-input i_clk,
-input i_rst, //reset when high
-//Wishbone Slave port
-input i_wb_cyc,
-input i_wb_stb,
-input i_wb_we,
-input [adr_wb_nb-1:0]i_wb_adr,
-input [wb_nb-1:0]i_wb_data,
-output o_wb_ack,
-output [wb_nb-1:0]o_wb_data,
-
-//u(n) output
-output [31:0]o_un,
-output o_valid
-);
-
-
-
-reg [15:0]kp,ki,kd,sp,pv;
-reg wla,wlb; // write locks
-wire wlRS;
-assign wlRS=wla|wlb;
-wire [0:7]wl={{3{wla}},{2{wlb}},3'h0};
-
-reg wack; //write acknowledged
-
-wire [2:0]adr; // address for write
-`ifdef wb_16bit
-assign adr=i_wb_adr[3:1];
-`endif
-`ifdef wb_32bit
-assign adr=i_wb_adr[4:2];
-`endif
-`ifdef wb_64bit
-assign adr=i_wb_adr[5:3];
-`endif
-
-wire [3:0]adr_1; // address for read
-`ifdef wb_32bit
-assign adr_1=i_wb_adr[5:2];
-`endif
-`ifdef wb_16bit
-assign adr_1=i_wb_adr[4:1];
-`endif
-`ifdef wb_64bit
-assign adr_1=i_wb_adr[6:3];
-`endif
-
-
-wire we; // write enable
-assign we=i_wb_cyc&i_wb_we&i_wb_stb;
-wire re; //read enable
-assign re=i_wb_cyc&(~i_wb_we)&i_wb_stb;
-
-reg state_0; //state machine No.1's state register
-
-wire adr_check_1; // A '1' means address is within the range of adr_1
-`ifdef wb_32bit
-assign adr_check_1=i_wb_adr[adr_wb_nb-1:6]==0;
-`endif
-`ifdef wb_16bit
-assign adr_check_1=i_wb_adr[adr_wb_nb-1:5]==0;
-`endif
-`ifdef wb_64bit
-assign adr_check_1=i_wb_adr[adr_wb_nb-1:7]==0;
-`endif
-
-wire adr_check; // A '1' means address is within the range of adr
-`ifdef wb_16bit
-assign adr_check=i_wb_adr[4]==0&&adr_check_1;
-`endif
-`ifdef wb_32bit
-assign adr_check=i_wb_adr[5]==0&&adr_check_1;
-`endif
-`ifdef wb_64bit
-assign adr_check=i_wb_adr[6]==0&&adr_check_1;
-`endif
-
- //state machine No.1
-reg RS;
-always@(posedge i_clk or posedge i_rst)
- if(i_rst)begin
- state_0<=0;
- wack<=0;
- kp<=0;
- ki<=0;
- kd<=0;
- sp<=0;
- pv<=0;
- RS<=0;
- end
- else begin
- if(wack&&(!i_wb_stb)) wack<=0;
- if(RS)RS<=0;
- case(state_0)
- 0: begin
- if(we&&(!wack)) state_0<=1;
- end
- 1: begin
- if(adr_check)begin
- if(!wl[adr])begin
- wack<=1;
- state_0<=0;
- case(adr)
- 0: begin
- kp<=i_wb_data[15:0];
- end
- 1: begin
- ki<=i_wb_data[15:0];
- end
- 2: begin
- kd<=i_wb_data[15:0];
- end
- 3: begin
- sp<=i_wb_data[15:0];
- end
- 4: begin
- pv<=i_wb_data[15:0];
- end
- endcase
-
- end
- end
- else if((adr_1==RS_adr)&&(!wlRS)&&(i_wb_data==0))begin
- wack<=1;
- state_0<=0;
- RS<=1;
- end
- else begin
- wack<=1;
- state_0<=0;
- end
- end
- endcase
- end
-
-
- //state machine No.2
-reg [9:0]state_1;
-
-wire update_kpd;
-assign update_kpd=wack&&(~adr[2])&&(~adr[0])&&adr_check; //adr==0||adr==2
-
-wire update_esu; //update e(n), sigma and u(n)
-assign update_esu=wack&&(adr==4)&&adr_check;
-
-reg rla; // read locks
-reg rlb;
-
-
-reg [4:0]of;
-reg [15:0]kpd;
-reg [15:0]err[0:1];
-
-wire [15:0]mr,md;
-
-reg [31:0]p;
-reg [31:0]a,sigma,un;
-
-reg cout;
-wire cin;
-wire [31:0]sum;
-wire [31:0]product;
-
-reg start; //start signal for multiplier
-
-reg [1:0]mr_index;
-reg [1:0]md_index;
-assign mr= mr_index==1?kpd:
- mr_index==2?kd:ki;
-assign md= md_index==2?err[1]:
- md_index==1?err[0]:sum[15:0];
-
-
-wire of_addition[0:1];
-assign of_addition[0]=(p[15]&&a[15]&&(!sum[15]))||((!p[15])&&(!a[15])&&sum[15]);
-assign of_addition[1]=(p[31]&&a[31]&&(!sum[31]))||((!p[31])&&(!a[31])&&sum[31]);
-
-always@(posedge i_clk or posedge i_rst)
- if(i_rst)begin
- state_1<=12'b000000000001;
- wla<=0;
- wlb<=0;
- rla<=0;
- rlb<=0;
- of<=0;
- kpd<=0;
- err[0]<=0;
- err[1]<=0;
- p<=0;
- a<=0;
- sigma<=0;
- un<=0;
- start<=0;
- mr_index<=0;
- md_index<=0;
- cout<=0;
- end
- else begin
- case(state_1)
- 10'b0000000001: begin
- if(update_kpd)begin
- state_1<=10'b0000000010;
- wla<=1;
- rla<=1;
- end
- else if(update_esu)begin
- state_1<=10'b0000001000;
- wla<=1;
- wlb<=1;
- rlb<=1;
- end
- else if(RS)begin //start a new sequance of U(n)
- un<=0;
- sigma<=0;
- of<=0;
- err[0]<=0;
- end
- end
- 10'b0000000010: begin
- p<={{16{kp[15]}},kp};
- a<={{16{kd[15]}},kd};
- state_1<=10'b0000000100;
- end
- 10'b0000000100: begin
- kpd<=sum[15:0];
- wla<=0;
- rla<=0;
- of[0]<=of_addition[0];
- state_1<=10'b0000000001;
- end
- 10'b0000001000: begin
- p<={{16{sp[15]}},sp};
- a<={{16{~pv[15]}},~pv};
- cout<=1;
- start<=1; // start calculate err0 * ki
- state_1<=10'b0000010000;
- end
- 10'b0000010000: begin
- err[0]<=sum[15:0];
- of[1]<=of_addition[0];
- of[2]<=of[1];
- p<={{16{~err[0][15]}},~err[0]};
- a<={31'b0,1'b1};
- cout<=0;
- mr_index<=1; // start calculate err0 * kpd
- md_index<=1;
- state_1<=10'b0000100000;
- end
- 10'b0000100000: begin
- err[1]<=sum[15:0];
- mr_index<=2; // start calculate err1 * kd
- md_index<=2;
- state_1<=10'b0001000000;
- end
- 10'b0001000000: begin
- mr_index<=0;
- md_index<=0;
- start<=0;
- p<=product; // start calculate err0*ki + sigma_last
- a<=sigma;
- state_1<=10'b0010000000;
- end
- 10'b0010000000: begin
- a<=sum; // start calculate err0*kpd + sigma_recent
- sigma<=sum;
- of[3]<=of[4]|of_addition[1];
- of[4]<=of[4]|of_addition[1];
- p<=product;
- state_1<=10'b0100000000;
- end
- 10'b0100000000: begin
- a<=sum; // start calculate err0*kpd + sigma_recent+err1*kd
- of[3]<=of[3]|of_addition[1];
- p<=product;
- state_1<=10'b1000000000;
- end
- 10'b1000000000: begin
- un<=sum;
- of[3]<=of[3]|of_addition[1];
- state_1<=10'b0000000001;
- wla<=0;
- wlb<=0;
- rlb<=0;
- end
- endcase
- end
-
-
-wire ready;
-multiplier_16x16bit_pipelined multiplier_16x16bit_pipelined(
-i_clk,
-~i_rst,
-start,
-md,
-mr,
-product,
-ready
-);
-
-adder_32bit adder_32bit_0(
-a,
-p,
-cout,
-sum,
-cin
-);
-
-
-wire [wb_nb-1:0]rdata[0:15]; //wishbone read data array
-`ifdef wb_16bit
-assign rdata[0]=kp;
-assign rdata[1]=ki;
-assign rdata[2]=kd;
-assign rdata[3]=sp;
-assign rdata[4]=pv;
-assign rdata[5]=kpd;
-assign rdata[6]=err[0];
-assign rdata[7]=err[1];
-assign rdata[8]=un[15:0];
-assign rdata[9]=sigma[15:0];
-assign rdata[10]={11'b0,of};
-`endif
-
-`ifdef wb_32bit
-assign rdata[0]={{16{kp[15]}},kp};
-assign rdata[1]={{16{ki[15]}},ki};
-assign rdata[2]={{16{kd[15]}},kd};
-assign rdata[3]={{16{sp[15]}},sp};
-assign rdata[4]={{16{pv[15]}},pv};
-assign rdata[5]={{16{kpd[15]}},kpd};
-assign rdata[6]={{16{err[0][15]}},err[0]};
-assign rdata[7]={{16{err[1][15]}},err[1]};
-assign rdata[8]=un;
-assign rdata[9]=sigma;
-assign rdata[10]={27'b0,of};
-`endif
-
-`ifdef wb_64bit
-assign rdata[0]={{48{kp[15]}},kp};
-assign rdata[1]={{48{ki[15]}},ki};
-assign rdata[2]={{48{kd[15]}},kd};
-assign rdata[3]={{48{sp[15]}},sp};
-assign rdata[4]={{48{pv[15]}},pv};
-assign rdata[5]={{48{kpd[15]}},kpd};
-assign rdata[6]={{48{err[0][15]}},err[0]};
-assign rdata[7]={{48{err[1][15]}},err[1]};
-assign rdata[8]={{32{un[31]}},un};
-assign rdata[9]={{32{sigma[31]}},sigma};
-assign rdata[10]={59'b0,of};
-`endif
-
-assign rdata[11]=0;
-assign rdata[12]=0;
-assign rdata[13]=0;
-assign rdata[14]=0;
-assign rdata[15]=0;
-
-
-wire [0:15]rl;
-assign rl={5'b0,rla,{4{rlb}},rla|rlb,5'b0};
-
-wire rack; // wishbone read acknowledged
-assign rack=(re&adr_check_1&(~rl[adr_1]))|(re&(~adr_check_1));
-
-assign o_wb_ack=(wack|rack)&i_wb_stb;
-
-assign o_wb_data=adr_check_1?rdata[adr_1]:0;
-assign o_un=un;
-assign o_valid=~rlb;
-
-
-endmodule
\ No newline at end of file
diff --git a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/PID_defines.v b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/PID_defines.v
deleted file mode 100644
index a43f6b38d..000000000
--- a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/PID_defines.v
+++ /dev/null
@@ -1,8 +0,0 @@
-//`define wb_16bit
-`define wb_32bit
-//`define wb_64bit
-
-
-//`define PID_test
-
-//`define PID_direct_test
\ No newline at end of file
diff --git a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/booth.v b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/booth.v
deleted file mode 100644
index f33b3d80e..000000000
--- a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/booth.v
+++ /dev/null
@@ -1,37 +0,0 @@
-/*Booth Encoder
-Author: Zhu Xu
-Email: m99a1@yahoo.cn
-*/
-module booth_radix4(
-input [2:0]codes,
-output zero,
-output double,
-output negation
-);
-
-wire A;
-assign A=codes[2];
-wire B;
-assign B=codes[1];
-wire C;
-assign C=codes[0];
-wire nB,nC,nA;
-assign nB=~B;
-assign nC=~C;
-assign nA=~A;
-
-wire BC;
-assign BC=B&C;
-wire nBnC;
-assign nBnC=nB&nC;
-wire nBanC;
-assign nBanC=nB|nC;
-
-assign double=(nBnC&A)|(BC&nA);
-assign negation=A&nBanC;
-assign zero=(A&BC)|(nA&nBnC);
-
-
-
-
-endmodule
\ No newline at end of file
diff --git a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/delay_gen_ihd_ipd_isd.v b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/delay_gen_ihd_ipd_isd.v
deleted file mode 100644
index ff94461cd..000000000
--- a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/delay_gen_ihd_ipd_isd.v
+++ /dev/null
@@ -1,207 +0,0 @@
-//==================================================================
-// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-// ------------------------------------------------------------------
-// Copyright (c) 2014 by Lattice Semiconductor Corporation
-// ALL RIGHTS RESERVED
-// ------------------------------------------------------------------
-//
-// Permission:
-//
-// Lattice SG Pte. Ltd. grants permission to use this code for use
-// in synthesis for any Lattice programmable logic product. Other
-// use of this code, including the selling or duplication of any
-// portion is strictly prohibited.
-
-//
-// Disclaimer:
-//
-// This VHDL or Verilog source code is intended as a design reference
-// which illustrates how these types of functions can be implemented.
-// It is the user's responsibility to verify their design for
-// consistency and functionality through the use of formal
-// verification methods. Lattice provides no warranty
-// regarding the use or functionality of this code.
-//
-// --------------------------------------------------------------------
-//
-// Lattice SG Pte. Ltd.
-// 101 Thomson Road, United Square #07-02
-// Singapore 307591
-//
-//
-// TEL: 1-800-Lattice (USA and Canada)
-// +65-6631-2000 (Singapore)
-// +1-503-268-8001 (other locations)
-//
-// web: http://www.latticesemi.com/
-// email: techsupport@latticesemi.com
-//
-// --------------------------------------------------------------------
-//
-
-
-module delay_gen_ihd_ipd_isd(
- input clk,
- input rst,
- input start_stop,
- input [15:0] isd_val,
- input [15:0] ipd_val,
- input config_reg_done,
- input symbol_shift_done,
- input packet_shift_done,
- input hop_shift_done,
- output reg isd_delay_en,
- output reg ipd_delay_en
-);
-
-reg [15:0] isd_val_temp;
-reg [15:0] ipd_val_temp;
-reg [15:0] isd_count;
-reg [15:0] ipd_count;
-wire [20:0] max_count;
-wire [20:0] max_count_pkt /* synthesis syn_multstyle = logic */;
-reg clk_count,clk_count_pkt;
-reg count_done,count_done_pkt;
-
-parameter const_fact=20;
-assign max_count=isd_val_temp * const_fact;
-assign max_count_pkt=ipd_val_temp * const_fact;
-
-//wire count_enable,count_enable_pkt;
-reg count_enable,count_enable_pkt;
-//wire config_done;
-//assign config_done= !rst_n ? 0 : config_reg_done ? 1 : config_done; //orignal
-//assign count_enable= rst ? 0 : count_done ? 0 : symbol_shift_done ? 1 : count_enable; //orignal
-//assign count_enable_pkt= rst ? 0 : count_done_pkt ? 0 : (packet_shift_done || hop_shift_done) ? 1 : count_enable_pkt;
-
-//assign isd_delay_en=symbol_shift_done ? 1 : (isd_count==max_count-1) :
-
-///////**********modified 11/feb/2014*************** /////////
- always @(posedge clk or posedge rst) begin
- if(rst || !start_stop) begin
- count_enable=0;
- end
- else begin
- if(count_done)
- count_enable=0;
- else if(symbol_shift_done)
- count_enable=1;
- else
- count_enable=count_enable;
-
- end
-end
-
-always @(posedge clk or posedge rst) begin
- if(rst || !start_stop) begin
- count_enable_pkt=0;
- end
- else begin
- if(count_done_pkt)
- count_enable_pkt=0;
- else if(packet_shift_done || hop_shift_done)
- count_enable_pkt=1;
- else
- count_enable_pkt=count_enable_pkt;
- end
-end
-
-/////////////////******************************//////////
-
-
-
-
-///////////////////////symbol////////////////////////////////////
-always @(posedge clk or posedge rst) begin
- if(rst || !start_stop) begin
- isd_count<=0;
- count_done<=0;
- isd_delay_en<=0;
- end
- else begin
- count_done<=0;
- if(count_enable) begin
- if(isd_count==max_count) begin
- isd_count<=0;
- count_done<=1;
- isd_delay_en<=0;
- end
- else begin
- isd_delay_en<=1;
- isd_count<=isd_count+1;
- end
- end
- else begin
- isd_delay_en<=0;
- isd_count<=0;
- end
- end
-end
-
-always @(posedge clk or posedge rst) begin
- if(rst || !start_stop) begin
- isd_val_temp<=0;
- clk_count<=0;
- end
- else begin
- if(!config_reg_done) begin
- isd_val_temp<=isd_val;
- clk_count<=0;
- end
- else if(config_reg_done) begin
- clk_count<=clk_count+1;
- isd_val_temp<=isd_val;
- end
- else begin
- isd_val_temp<=isd_val_temp;
- end
- end
-end
-///////////////packet//////////////////////
-always @(posedge clk or posedge rst) begin
- if(rst || !start_stop) begin
- ipd_count<=0;
- count_done_pkt<=0;
- ipd_delay_en<=0;
- end
- else begin
- count_done_pkt<=0;
- if(count_enable_pkt) begin
- if(ipd_count==max_count_pkt) begin
- ipd_count<=0;
- count_done_pkt<=1;
- ipd_delay_en<=0;
- end
- else begin
- ipd_delay_en<=1;
- ipd_count<=ipd_count+1;
- end
- end
- else begin
- ipd_delay_en<=0;
- ipd_count<=0;
- end
- end
-end
-
-always @(posedge clk or posedge rst) begin
- if(rst || !start_stop) begin
- ipd_val_temp<=0;
- clk_count_pkt<=0;
- end
-else begin
- if(!config_reg_done) begin
- ipd_val_temp<=ipd_val;
- clk_count_pkt<=0;
- end
- else if(config_reg_done) begin
- clk_count_pkt<=clk_count_pkt+1;
- ipd_val_temp<=ipd_val;
- end
- else begin // if(!config_reg_done) begin
- ipd_val_temp<=ipd_val_temp;
- end
- end
-end
-
-endmodule
diff --git a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/i2c_defines.v b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/i2c_defines.v
deleted file mode 100644
index a1ccc5fdc..000000000
--- a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/i2c_defines.v
+++ /dev/null
@@ -1,369 +0,0 @@
-//==================================================================
-// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-// ------------------------------------------------------------------
-// Copyright (c) 2014 by Lattice Semiconductor Corporation
-// ALL RIGHTS RESERVED
-// ------------------------------------------------------------------
-//
-// Permission:
-//
-// Lattice SG Pte. Ltd. grants permission to use this code for use
-// in synthesis for any Lattice programmable logic product. Other
-// use of this code, including the selling or duplication of any
-// portion is strictly prohibited.
-
-//
-// Disclaimer:
-//
-// This VHDL or Verilog source code is intended as a design reference
-// which illustrates how these types of functions can be implemented.
-// It is the user's responsibility to verify their design for
-// consistency and functionality through the use of formal
-// verification methods. Lattice provides no warranty
-// regarding the use or functionality of this code.
-//
-// --------------------------------------------------------------------
-//
-// Lattice SG Pte. Ltd.
-// 101 Thomson Road, United Square #07-02
-// Singapore 307591
-//
-//
-// TEL: 1-800-Lattice (USA and Canada)
-// +65-6631-2000 (Singapore)
-// +1-503-268-8001 (other locations)
-//
-// web: http://www.latticesemi.com/
-// email: techsupport@latticesemi.com
-//
-// --------------------------------------------------------------------
-//
-
-
-
-/***********************************************************************
- * *
- * EFB REGISTER SET *
- * *
- ***********************************************************************/
-
-
-`define MICO_EFB_I2C_CR 8'h08
-`define MICO_EFB_I2C_CMDR 8'h09
-`define MICO_EFB_I2C_BLOR 8'h0a
-`define MICO_EFB_I2C_BHIR 8'h0b
-`define MICO_EFB_I2C_TXDR 8'h0d
-`define MICO_EFB_I2C_SR 8'h0c
-`define MICO_EFB_I2C_GCDR 8'h0f
-`define MICO_EFB_I2C_RXDR 8'h0e
-`define MICO_EFB_I2C_IRQSR 8'h06
-`define MICO_EFB_I2C_IRQENR 8'h09
-
-/***********************************************************************
- * *
- * EFB I2C CONTROLLER PHYSICAL DEVICE SPECIFIC INFORMATION *
- * *
- ***********************************************************************/
-
-
-
-// Control Register Bit Masks
-`define MICO_EFB_I2C_CR_I2CEN 8'h80
-`define MICO_EFB_I2C_CR_GCEN 8'h40
-`define MICO_EFB_I2C_CR_WKUPEN 8'h20
-// Status Register Bit Masks
-`define MICO_EFB_I2C_SR_TIP 8'h80
-`define MICO_EFB_I2C_SR_BUSY 8'h40
-`define MICO_EFB_I2C_SR_RARC 8'h20
-`define MICO_EFB_I2C_SR_SRW 8'h10
-`define MICO_EFB_I2C_SR_ARBL 8'h08
-`define MICO_EFB_I2C_SR_TRRDY 8'h04
-`define MICO_EFB_I2C_SR_TROE 8'h02
-`define MICO_EFB_I2C_SR_HGC 8'h01
-// Command Register Bit Masks
-`define MICO_EFB_I2C_CMDR_STA 8'h80
-`define MICO_EFB_I2C_CMDR_STO 8'h40
-`define MICO_EFB_I2C_CMDR_RD 8'h20
-`define MICO_EFB_I2C_CMDR_WR 8'h10
-`define MICO_EFB_I2C_CMDR_NACK 8'h08
-`define MICO_EFB_I2C_CMDR_CKSDIS 8'h04
-
-
-/***********************************************************************
- * *
- * CODE SPECIFIC *
- * *
- ***********************************************************************/
-
- `define ALL_ZERO 8'h00
- `define READ 1'b0
- `define READ 1'b0
- `define HIGH 1'b1
- `define WRITE 1'b1
- `define LOW 1'b0
- `define READ_STATUS 1'b0
- `define READ_DATA 1'b0
-
-/***********************************************************************
- * *
- * State Machine Variables *
- * *
- ***********************************************************************/
-
-`define state0 8'd00
-`define state1 8'd01
-`define state2 8'd02
-`define state3 8'd03
-`define state4 8'd04
-`define state5 8'd05
-`define state6 8'd06
-`define state7 8'd07
-`define state8 8'd08
-`define state9 8'd09
-`define state10 8'd10
-`define state11 8'd11
-`define state12 8'd12
-`define state13 8'd13
-`define state14 8'd14
-`define state15 8'd15
-`define state16 8'd16
-`define state17 8'd17
-`define state18 8'd18
-`define state19 8'd19
-`define state20 8'd20
-`define state21 8'd21
-`define state22 8'd22
-`define state23 8'd23
-`define state24 8'd24
-`define state25 8'd25
-`define state26 8'd26
-`define state27 8'd27
-`define state28 8'd28
-`define state29 8'd29
-`define state30 8'd30
-`define state31 8'd31
-`define state32 8'd32
-`define state33 8'd33
-`define state34 8'd34
-`define state35 8'd35
-`define state36 8'd36
-`define state37 8'd37
-`define state38 8'd38
-`define state39 8'd39
-`define state40 8'd40
-`define state41 8'd41
-`define state42 8'd42
-`define state43 8'd43
-`define state44 8'd44
-`define state45 8'd45
-`define state46 8'd46
-`define state47 8'd47
-`define state48 8'd48
-`define state49 8'd49
-`define state50 8'd50
-`define state51 8'd51
-`define state52 8'd52
-`define state53 8'd53
-`define state54 8'd54
-`define state55 8'd55
-`define state56 8'd56
-`define state57 8'd57
-`define state58 8'd58
-`define state59 8'd59
-`define state60 8'd60
-`define state61 8'd61
-`define state62 8'd62
-`define state63 8'd63
-`define state64 8'd64
-`define state65 8'd65
-`define state66 8'd66
-`define state67 8'd67
-`define state68 8'd68
-`define state69 8'd69
-`define state70 8'd70
-`define state71 8'd71
-`define state72 8'd72
-`define state73 8'd73
-`define state74 8'd74
-`define state75 8'd75
-`define state76 8'd76
-`define state77 8'd77
-`define state78 8'd78
-`define state79 8'd79
-`define state80 8'd80
-`define state81 8'd81
-`define state82 8'd82
-`define state83 8'd83
-`define state84 8'd84
-`define state85 8'd85
-`define state86 8'd86
-`define state87 8'd87
-`define state88 8'd88
-`define state89 8'd89
-`define state90 8'd90
-`define state91 8'd91
-`define state92 8'd92
-`define state93 8'd93
-`define state94 8'd94
-`define state95 8'd95
-`define state96 8'd96
-`define state97 8'd97
-`define state98 8'd98
-`define state99 8'd99
-`define state100 8'd100
-`define state101 8'd101
-`define state102 8'd102
-`define state103 8'd103
-`define state104 8'd104
-`define state105 8'd105
-`define state106 8'd106
-`define state107 8'd107
-`define state108 8'd108
-`define state109 8'd109
-`define state110 8'd110
-`define state111 8'd111
-`define state112 8'd112
-`define state113 8'd113
-`define state114 8'd114
-`define state115 8'd115
-`define state116 8'd116
-`define state117 8'd117
-`define state118 8'd118
-`define state119 8'd119
-`define state120 8'd120
-`define state121 8'd121
-`define state122 8'd122
-`define state123 8'd123
-`define state124 8'd124
-`define state125 8'd125
-`define state126 8'd126
-`define state127 8'd127
-`define state128 8'd128
-`define state129 8'd129
-`define state130 8'd130
-`define state131 8'd131
-`define state132 8'd132
-`define state133 8'd133
-`define state134 8'd134
-`define state135 8'd135
-`define state136 8'd136
-`define state137 8'd137
-`define state138 8'd138
-`define state139 8'd139
-`define state140 8'd140
-`define state141 8'd141
-`define state142 8'd142
-`define state143 8'd143
-`define state144 8'd144
-`define state145 8'd145
-`define state146 8'd146
-`define state147 8'd147
-`define state148 8'd148
-`define state149 8'd149
-`define state150 8'd150
-`define state151 8'd151
-`define state152 8'd152
-`define state153 8'd153
-`define state154 8'd154
-`define state155 8'd155
-`define state156 8'd156
-`define state157 8'd157
-`define state158 8'd158
-`define state159 8'd159
-`define state160 8'd160
-`define state161 8'd161
-`define state162 8'd162
-`define state163 8'd163
-`define state164 8'd164
-`define state165 8'd165
-`define state166 8'd166
-`define state167 8'd167
-`define state168 8'd168
-`define state169 8'd169
-`define state170 8'd170
-`define state171 8'd171
-`define state172 8'd172
-`define state173 8'd173
-`define state174 8'd174
-`define state175 8'd175
-`define state176 8'd176
-`define state177 8'd177
-`define state178 8'd178
-`define state179 8'd179
-`define state180 8'd180
-`define state181 8'd181
-`define state182 8'd182
-`define state183 8'd183
-`define state184 8'd184
-`define state185 8'd185
-`define state186 8'd186
-`define state187 8'd187
-`define state188 8'd188
-`define state189 8'd189
-`define state190 8'd190
-`define state191 8'd191
-`define state192 8'd192
-`define state193 8'd193
-`define state194 8'd194
-`define state195 8'd195
-`define state196 8'd196
-`define state197 8'd197
-`define state198 8'd198
-`define state199 8'd199
-`define state200 8'd200
-`define state201 8'd201
-`define state202 8'd202
-`define state203 8'd203
-`define state204 8'd204
-`define state205 8'd205
-`define state206 8'd206
-`define state207 8'd207
-`define state208 8'd208
-`define state209 8'd209
-`define state210 8'd210
-`define state211 8'd211
-`define state212 8'd212
-`define state213 8'd213
-`define state214 8'd214
-`define state215 8'd215
-`define state216 8'd216
-`define state217 8'd217
-`define state218 8'd218
-`define state219 8'd219
-`define state220 8'd220
-`define state221 8'd221
-`define state222 8'd222
-`define state223 8'd223
-`define state224 8'd224
-`define state225 8'd225
-`define state226 8'd226
-`define state227 8'd227
-`define state228 8'd228
-`define state229 8'd229
-`define state230 8'd230
-`define state231 8'd231
-`define state232 8'd232
-`define state233 8'd233
-`define state234 8'd234
-`define state235 8'd235
-`define state236 8'd236
-`define state237 8'd237
-`define state238 8'd238
-`define state239 8'd239
-`define state240 8'd240
-`define state241 8'd241
-`define state242 8'd242
-`define state243 8'd243
-`define state244 8'd244
-`define state245 8'd245
-`define state246 8'd246
-`define state247 8'd247
-`define state248 8'd248
-`define state249 8'd249
-`define state250 8'd250
-`define state251 8'd251
-`define state252 8'd252
-`define state253 8'd253
-`define state254 8'd254
-`define state255 8'd255
-
diff --git a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/i2c_slave_data_fsm.v b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/i2c_slave_data_fsm.v
deleted file mode 100644
index e1aac59ec..000000000
--- a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/i2c_slave_data_fsm.v
+++ /dev/null
@@ -1,649 +0,0 @@
-//==================================================================
-// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-// ------------------------------------------------------------------
-// Copyright (c) 2014 by Lattice Semiconductor Corporation
-// ALL RIGHTS RESERVED
-// ------------------------------------------------------------------
-//
-// Permission:
-//
-// Lattice SG Pte. Ltd. grants permission to use this code for use
-// in synthesis for any Lattice programmable logic product. Other
-// use of this code, including the selling or duplication of any
-// portion is strictly prohibited.
-
-//
-// Disclaimer:
-//
-// This VHDL or Verilog source code is intended as a design reference
-// which illustrates how these types of functions can be implemented.
-// It is the user's responsibility to verify their design for
-// consistency and functionality through the use of formal
-// verification methods. Lattice provides no warranty
-// regarding the use or functionality of this code.
-//
-// --------------------------------------------------------------------
-//
-// Lattice SG Pte. Ltd.
-// 101 Thomson Road, United Square #07-02
-// Singapore 307591
-//
-//
-// TEL: 1-800-Lattice (USA and Canada)
-// +65-6631-2000 (Singapore)
-// +1-503-268-8001 (other locations)
-//
-// web: http://www.latticesemi.com/
-// email: techsupport@latticesemi.com
-//
-// --------------------------------------------------------------------
-//
-
-`include "i2c_defines.v"
-`include "i2c_new_reg.v"
-`timescale 1 ns / 1 ns
-
-
-module serialInterface (/*AUTOARG*/
- // Outputs
- dataOut, regAddr, sdaOut, writeEn, readEn, i2c_start,
- // Inputs
- clk, dataIn, rst, scl, sdaIn
- );
- input clk;
- input [7:0] dataIn;
- input rst;
- input scl;
- input sdaIn;
- output [7:0] dataOut;
- output [7:0] regAddr;
- output sdaOut;
- output writeEn;
- output readEn;
- output i2c_start;
-
- // I2C_SLAVE_INIT_ADDR: Upper Bits <9:2> can be changed. Lower bits <1:0> are fixed.
- // For I2C Hard IP located in Upper Left <1:0> must be set to "01".
- // For I2C Hard IP located in Upper Right <1:0> must be set to "10".
- parameter I2C_SLAVE_INIT_ADDR = "0b1111100001"; //Upper Left
- //parameter I2C_SLAVE_INIT_ADDR = "0b1111100010"; //Upper Right
-
- // BUS_ADDR74: Fixed value. SBADRI [7:4] bits also should match with this value to
- // activate the IP.
- // For I2C Hard IP located in Upper Left [7:4] must be set to "0001".
- // For I2C Hard IP located in Upper Right [7:4] must be set to "0011".
- parameter BUS_ADDR74_STRING = "0b0001"; //Upper Left
- //parameter BUS_ADDR74_STRING = "0b0011"; //Upper Right
-
- // These are for the "OR" function with "wb_adr_i". Note that bits [7:4] are copies
- // of BUS_ADDR74_STRING.
- parameter BUS_ADDR74 = 8'b0001_0000; //Upper Left
- //parameter BUS_ADDR74 = 8'b0011_0000; //Upper Right
-
- reg [7:0] regAddr;
- reg writeEn;
- wire [7:0] dataOut;
- reg i2c_start;
-
- /*
- * System bus interface signals
- */
- reg [7:0] wb_dat_i;
- reg wb_stb_i;
- reg [7:0] wb_adr_i;
- reg wb_we_i;
- wire [7:0] wb_dat_o;
- wire wb_ack_o;
- /*
- * Data Read and Write Register
- */
- reg [7:0] temp0;
- reg [7:0] temp1;
- reg [7:0] temp2;
- reg [7:0] temp3;
- reg [7:0] n_temp0;
- reg [7:0] n_temp1;
- reg [7:0] n_temp2;
- reg [7:0] n_temp3;
- reg readEn;
-
-
- /*
- * i2c Module Instanitiation
- */
-
-
- i2c UUT1 (
- .wb_clk_i (clk),
- .wb_dat_i (wb_dat_i),
- .wb_stb_i (wb_stb_i),
- .wb_adr_i (wb_adr_i | BUS_ADDR74),
- .wb_we_i (wb_we_i),
- .wb_dat_o (wb_dat_o),
- .wb_ack_o (wb_ack_o),
- .i2c_irqo ( ),
- .i2c_scl (scl),
- .i2c_sda (sdaOut),
- .i2c_sda_in (sdaIn),
- .rst_i(rst)
- );
-
- defparam UUT1.I2C_SLAVE_INIT_ADDR = I2C_SLAVE_INIT_ADDR;
- defparam UUT1.BUS_ADDR74_STRING = BUS_ADDR74_STRING;
-
- /*
- * Signal & wire Declartion
- */
- reg efb_flag;
- reg n_efb_flag;
- reg [7:0] n_wb_dat_i;
- reg n_wb_stb_i;
- reg [7:0] n_wb_adr_i;
- reg n_wb_we_i;
- reg [7:0] c_state;
- reg [7:0] n_state;
- reg n_count_en;
- reg count_en;
- wire invalid_command = 0;
-
- /*
- * Output generation
- */
-
- assign dataOut = temp3;
-
- always @(posedge clk or posedge rst)begin
- if (rst)begin
- writeEn <= 0;
- readEn <= 0;
- end else begin
- if(c_state == `state14)begin
- writeEn <= 1'b1;
- end else begin
- writeEn <= 1'b0;
- end
-
- if(c_state == `state15)begin
- readEn <= 1'b1;
- end else if (c_state == `state13) begin //**
- if (n_temp2 & (`MICO_EFB_I2C_SR_SRW)) begin
- readEn <= 1'b1;
- end else begin
- readEn <= 1'b0;
- end
- end else begin
- readEn <= 1'b0;
- end
- end
- end
-
- always @(posedge clk or posedge rst)begin
- if (rst)begin
- regAddr <= 0;
- end else begin
- if(c_state == `state2)begin
- regAddr <= 8'd0;
- end else if(c_state == `state9)begin
- regAddr <= temp1;
- //end else if(writeEn || readEn)begin
- // regAddr <= regAddr + 1;
- end
- end
- end
-
- //slave start detect
- always @(posedge clk or posedge rst) begin
- if (rst) begin
- i2c_start <= 0;
- end else begin
- if (c_state == `state12) begin
- i2c_start <= 0;
- end else if (c_state == `state9) begin
- i2c_start <= 1;
- end
- end
- end
-
- /*
- * Main state machine
- */
- always @ (posedge clk or posedge rst) begin
- if(rst) begin
- wb_dat_i <= 8'h00;
- wb_stb_i <= 1'b0 ;
- wb_adr_i <= 8'h00;
- wb_we_i <= 1'b0;
- end else begin
- wb_dat_i <= #1 n_wb_dat_i;
- wb_stb_i <= #1 n_wb_stb_i;
- wb_adr_i <= #1 n_wb_adr_i;
- wb_we_i <= #1 n_wb_we_i ;
- end
- end
-
- always @ (posedge clk or posedge rst) begin
- if(rst) begin
- c_state <= 10'h000;
- efb_flag <= 1'b0 ;
- count_en <= 1'b0;
- end else begin
- c_state <= n_state ;
- efb_flag <= n_efb_flag;
- count_en <= n_count_en;
- end
- end
-
- always @ (posedge clk or posedge rst) begin
- if(rst) begin
- temp0 <= 8'h00 ;
- temp1 <= 8'h00 ;
- temp2 <= 8'h00 ;
- temp3 <= 8'h00 ;
- end else begin
- temp0 <= n_temp0 ;
- temp1 <= n_temp1 ;
- temp2 <= n_temp2 ;
- temp3 <= n_temp3 ;
- end
- end
-
- always @(posedge clk or posedge rst) begin
- if (rst) begin
- n_temp2 <= 0;
- end else begin
- n_temp2 <= wb_dat_o; //**
- end
- end
-
- /*
- * FSM combinational block
- */
- always @ ( * ) begin
- n_efb_flag = 1'b0 ;
- n_state = c_state ;
- n_wb_dat_i = 8'h00;
- n_wb_stb_i = 1'b0 ;
- n_wb_adr_i = 8'h00;
- n_wb_we_i = 1'b0;
- n_count_en = 1'b0;
- n_temp0 = temp0;
- n_temp1 = temp1;
- n_temp3 = temp3;
-
- case(c_state)
- `state0: begin
- n_wb_dat_i = 8'h00;
- n_wb_stb_i = 1'b0 ;
- n_wb_adr_i = 8'h00;
- n_wb_we_i = 1'b0;
- n_wb_stb_i = 1'b0 ;
- n_state = `state1 ;
- end
-
- `state1: begin // Enable I2C Interface
- if (wb_ack_o && efb_flag) begin
- n_wb_dat_i = `ALL_ZERO ;
- n_wb_adr_i = `ALL_ZERO ;
- n_wb_we_i = `LOW ;
- n_wb_stb_i = `LOW ;
- n_efb_flag = `LOW ;
- n_count_en = `LOW ;
- n_state = `state2;
- end else begin
- n_efb_flag = `HIGH ;
- n_wb_we_i = `WRITE;
- n_wb_adr_i = `MICO_EFB_I2C_CR;
- n_wb_dat_i = 8'h80;
- n_wb_stb_i = `HIGH ;
- n_state = c_state;
- end
- end
-
-
- `state2: begin // Clock Disable
- if (wb_ack_o && efb_flag) begin
- n_wb_dat_i = `ALL_ZERO ;
- n_wb_adr_i = `ALL_ZERO ;
- n_wb_we_i = `LOW ;
- n_wb_stb_i = `LOW ;
- n_efb_flag = `LOW ;
- n_count_en = `LOW ;
- n_state = `state3;
- end else begin
- n_efb_flag = `HIGH ;
- n_wb_we_i = `WRITE;
- n_wb_adr_i = `MICO_EFB_I2C_CMDR;
- n_wb_dat_i = 8'h04;
- n_wb_stb_i = `HIGH ;
- n_state = c_state;
- end
- end
-
-
- `state3: begin // Wait for not BUSY
- if (wb_ack_o && efb_flag) begin
- n_wb_dat_i = `ALL_ZERO ;
- n_wb_adr_i = `ALL_ZERO ;
- n_wb_we_i = `LOW ;
- n_wb_stb_i = `LOW ;
- n_efb_flag = `LOW ;
- n_count_en = `LOW ;
- if(wb_dat_o & (`MICO_EFB_I2C_SR_BUSY))begin
- n_state = `state4;
- end else begin
- n_state = c_state;
- end
- end else begin
- n_efb_flag = `HIGH ;
- n_wb_we_i = `READ_STATUS;
- n_wb_adr_i = `MICO_EFB_I2C_SR;
- n_wb_dat_i = 0 ;
- n_wb_stb_i = `HIGH ;
- n_state = c_state;
- end
- end
-
-
- `state4: begin // Discard data 1
- if (wb_ack_o && efb_flag) begin
- n_wb_dat_i = `ALL_ZERO ;
- n_wb_adr_i = `ALL_ZERO ;
- n_wb_we_i = `LOW ;
- n_wb_stb_i = `LOW ;
- n_efb_flag = `LOW ;
- n_count_en = `LOW ;
- n_temp0 = wb_dat_o;
- n_state = `state5;
- end else begin
- n_efb_flag = `HIGH ;
- n_wb_we_i = `READ_DATA;
- n_wb_adr_i = `MICO_EFB_I2C_RXDR;
- n_wb_dat_i = 0 ;
- n_wb_stb_i = `HIGH ;
- n_state = c_state;
- end
- end
-
-
- `state5: begin // Discard data 2
- if (wb_ack_o && efb_flag) begin
- n_wb_dat_i = `ALL_ZERO ;
- n_wb_adr_i = `ALL_ZERO ;
- n_wb_we_i = `LOW ;
- n_wb_stb_i = `LOW ;
- n_efb_flag = `LOW ;
- n_count_en = `LOW ;
- n_temp0 = wb_dat_o;
- n_state = `state6;
- end else begin
- n_efb_flag = `HIGH ;
- n_wb_we_i = `READ_DATA;
- n_wb_adr_i = `MICO_EFB_I2C_RXDR;
- n_wb_dat_i = 0 ;
- n_wb_stb_i = `HIGH ;
- n_state = c_state;
- end
- end
-
-
- `state6: begin // Clock Enable
- if (wb_ack_o && efb_flag) begin
- n_wb_dat_i = `ALL_ZERO ;
- n_wb_adr_i = `ALL_ZERO ;
- n_wb_we_i = `LOW ;
- n_wb_stb_i = `LOW ;
- n_efb_flag = `LOW ;
- n_count_en = `LOW ;
- n_state = `state7;
- end else begin
- n_efb_flag = `HIGH;
- n_wb_we_i = `WRITE;
- n_wb_adr_i = `MICO_EFB_I2C_CMDR;
- n_wb_dat_i = 8'h00;
- n_wb_stb_i = `HIGH ;
- n_state = c_state;
- end
- end
-
-
- `state7: begin // wait for data to come
- if (wb_ack_o && efb_flag) begin
- n_wb_dat_i = `ALL_ZERO ;
- n_wb_adr_i = `ALL_ZERO ;
- n_wb_we_i = `LOW ;
- n_wb_stb_i = `LOW ;
- n_efb_flag = `LOW ;
- n_count_en = `LOW ;
- n_temp1 = 8'h00;
- if((wb_dat_o & (`MICO_EFB_I2C_SR_TRRDY)))begin
- n_state = `state8; // Slave acknowledged
- end else if (~wb_dat_o[6])begin
- n_state = `state2; // Disable clock
- end else begin
- n_state = c_state;
- end
- end else begin
- n_efb_flag = `HIGH ;
- n_wb_we_i = `READ_STATUS;
- n_wb_adr_i = `MICO_EFB_I2C_SR;
- n_wb_dat_i = 0 ;
- n_wb_stb_i = `HIGH ;
- n_state = c_state;
- end
- end
-
-
- `state8: begin // Store i2C Command Information
- if (wb_ack_o && efb_flag) begin
- n_wb_dat_i = `ALL_ZERO ;
- n_wb_adr_i = `ALL_ZERO ;
- n_wb_we_i = `LOW ;
- n_wb_stb_i = `LOW ;
- n_efb_flag = `LOW ;
- n_count_en = `LOW ;
- n_temp1 = wb_dat_o;
- n_state = `state9;
- end else begin
- n_efb_flag = `HIGH ;
- n_wb_we_i = `READ_DATA;
- n_wb_adr_i = `MICO_EFB_I2C_RXDR;
- n_wb_dat_i = 0 ;
- n_wb_stb_i = `HIGH ;
- n_state = c_state;
- end
- end
-
-
- `state9: begin // Send ACK or NACK Based upon Command Receive & Wait for Stop `state 17
- if (wb_ack_o && efb_flag) begin
- n_wb_dat_i = `ALL_ZERO ;
- n_wb_adr_i = `ALL_ZERO ;
- n_wb_we_i = `LOW ;
- n_wb_stb_i = `LOW ;
- n_efb_flag = `LOW ;
- n_count_en = `LOW ;
- if(invalid_command)begin // This is tied to '0' at present
- n_state = `state17;
- end else begin
- n_state = `state12;
- end
- end else begin
- n_efb_flag = `HIGH ;
- n_wb_we_i = `WRITE;
- n_wb_adr_i = `MICO_EFB_I2C_CMDR;
- n_wb_dat_i = {4'h0,invalid_command,3'b000};
- n_wb_stb_i = `HIGH ;
- n_state = c_state;
- end
- end
-
-
- `state12: begin // Wait for TRRDY Bit
- if (wb_ack_o && efb_flag) begin
- n_wb_dat_i = `ALL_ZERO ;
- n_wb_adr_i = `ALL_ZERO ;
- n_wb_we_i = `LOW ;
- n_wb_stb_i = `LOW ;
- n_efb_flag = `LOW ;
- n_count_en = `LOW ;
- if(wb_dat_o & (`MICO_EFB_I2C_SR_TRRDY))begin
- n_state = `state13;
- end else if (~wb_dat_o[6])begin
- n_state = `state2;
- end else begin
- n_state = c_state;
- end
- end else begin
- n_efb_flag = `HIGH ;
- n_wb_we_i = `READ_STATUS;
- n_wb_adr_i = `MICO_EFB_I2C_SR;
- n_wb_dat_i = 0 ;
- n_wb_stb_i = `HIGH ;
- n_state = c_state;
- end
- end
-
-
- `state13: begin // Check for read or write operation
- if (wb_ack_o && efb_flag) begin
- n_wb_dat_i = `ALL_ZERO ;
- n_wb_adr_i = `ALL_ZERO ;
- n_wb_we_i = `LOW ;
- n_wb_stb_i = `LOW ;
- n_efb_flag = `LOW ;
- n_count_en = `LOW ;
- if(wb_dat_o & (`MICO_EFB_I2C_SR_SRW))begin
- n_state = `state15; //Read from slave
- end else begin
- n_state = `state14; //Write to slave
- end
- end else begin
- n_efb_flag = `HIGH ;
- n_wb_we_i = `READ_STATUS;
- n_wb_adr_i = `MICO_EFB_I2C_SR;
- n_wb_dat_i = 0 ;
- n_wb_stb_i = `HIGH ;
- n_state = c_state;
- end
- end
-
-
- `state14: begin // Write data
- if (wb_ack_o && efb_flag) begin
- n_wb_dat_i = `ALL_ZERO ;
- n_wb_adr_i = `ALL_ZERO ;
- n_wb_we_i = `LOW ;
- n_wb_stb_i = `LOW ;
- n_efb_flag = `LOW ;
- n_count_en = `LOW ;
- n_temp3 = wb_dat_o;
- n_state = `state19;
- end else begin
- n_efb_flag = `HIGH ;
- n_wb_we_i = `READ_DATA;
- n_wb_adr_i = `MICO_EFB_I2C_RXDR;
- n_wb_dat_i = 0 ;
- n_wb_stb_i = `HIGH ;
- n_state = c_state;
- end
- end
-
-
- `state15: begin // Send Data to Master
- if (wb_ack_o && efb_flag) begin
- n_wb_dat_i = `ALL_ZERO ;
- n_wb_adr_i = `ALL_ZERO ;
- n_wb_we_i = `LOW ;
- n_wb_stb_i = `LOW ;
- n_efb_flag = `LOW ;
- n_count_en = `LOW ;
- n_state = `state18;
- end else begin
- n_efb_flag = `HIGH ;
- n_wb_we_i = `WRITE;
- n_wb_adr_i = `MICO_EFB_I2C_TXDR;
- n_wb_dat_i = dataIn;
- n_wb_stb_i = `HIGH ;
- n_state = c_state;
- end
- end
-
-
- `state17: begin // Wait till Stop is Send
- if (wb_ack_o && efb_flag) begin
- n_wb_dat_i = `ALL_ZERO ;
- n_wb_adr_i = `ALL_ZERO ;
- n_wb_we_i = `LOW ;
- n_wb_stb_i = `LOW ;
- n_efb_flag = `LOW ;
- n_count_en = `LOW ;
- if(~wb_dat_o[6])begin
- n_state = `state2;
- end else begin
- n_state = c_state;
- end
- end else begin
- n_efb_flag = `HIGH ;
- n_wb_we_i = `READ_STATUS;
- n_wb_adr_i = `MICO_EFB_I2C_SR;
- n_wb_dat_i = 0 ;
- n_wb_stb_i = `HIGH ;
- n_state = c_state;
- end
- end
-
- `state18: begin // Wait for TxRDY flag and send data again if required
- if (wb_ack_o && efb_flag) begin
- n_wb_dat_i = `ALL_ZERO ;
- n_wb_adr_i = `ALL_ZERO ;
- n_wb_we_i = `LOW ;
- n_wb_stb_i = `LOW ;
- n_efb_flag = `LOW ;
- n_count_en = `LOW ;
- if(wb_dat_o & (`MICO_EFB_I2C_SR_TRRDY))begin
- n_state = `state15; // Send Data
- end else if (~wb_dat_o[6]) begin// If Stop go to beginning
- n_state = `state2;
- end else begin
- n_state = c_state;
- end
- end else begin
- n_efb_flag = `HIGH ;
- n_wb_we_i = `READ_STATUS;
- n_wb_adr_i = `MICO_EFB_I2C_SR;
- n_wb_dat_i = 0 ;
- n_wb_stb_i = `HIGH ;
- n_state = c_state;
- end
- end
-
-
- `state19: begin // Wait for TRRDY bit
- if (wb_ack_o && efb_flag) begin
- n_wb_dat_i = `ALL_ZERO ;
- n_wb_adr_i = `ALL_ZERO ;
- n_wb_we_i = `LOW ;
- n_wb_stb_i = `LOW ;
- n_efb_flag = `LOW ;
- n_count_en = `LOW ;
- if(wb_dat_o & (`MICO_EFB_I2C_SR_TRRDY)) begin
- n_state = `state14;
- end else if (~wb_dat_o[6])begin
- n_state = `state2;
- end else begin
- n_state = c_state;
- end
- end else begin
- n_efb_flag = `HIGH ;
- n_wb_we_i = `READ_STATUS;
- n_wb_adr_i = `MICO_EFB_I2C_SR;
- n_wb_dat_i = 0 ;
- n_wb_stb_i = `HIGH ;
- n_state = c_state;
- end
- end
- endcase
- end
-
-
-endmodule
diff --git a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/led_driver_19022014.v b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/led_driver_19022014.v
deleted file mode 100644
index 0ca379453..000000000
--- a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/led_driver_19022014.v
+++ /dev/null
@@ -1,203 +0,0 @@
-//==================================================================
-// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-// ------------------------------------------------------------------
-// Copyright (c) 2014 by Lattice Semiconductor Corporation
-// ALL RIGHTS RESERVED
-// ------------------------------------------------------------------
-//
-// Permission:
-//
-// Lattice SG Pte. Ltd. grants permission to use this code for use
-// in synthesis for any Lattice programmable logic product. Other
-// use of this code, including the selling or duplication of any
-// portion is strictly prohibited.
-
-//
-// Disclaimer:
-//
-// This VHDL or Verilog source code is intended as a design reference
-// which illustrates how these types of functions can be implemented.
-// It is the user's responsibility to verify their design for
-// consistency and functionality through the use of formal
-// verification methods. Lattice provides no warranty
-// regarding the use or functionality of this code.
-//
-// --------------------------------------------------------------------
-//
-// Lattice SG Pte. Ltd.
-// 101 Thomson Road, United Square #07-02
-// Singapore 307591
-//
-//
-// TEL: 1-800-Lattice (USA and Canada)
-// +65-6631-2000 (Singapore)
-// +1-503-268-8001 (other locations)
-//
-// web: http://www.latticesemi.com/
-// email: techsupport@latticesemi.com
-//
-// --------------------------------------------------------------------
-//
-
-
-module led_driver (
- input sys_clk,
- input rst_n,
- input txn_start,
- input mobeam_start_stop,
- input led_polarity,
- input [7:0] bar_width,
- input [7:0] barcode_array,
- output drive_on,
- output byte_done,
- output bit_done,
- output oled
- //output dynamic_clk);
- );
-
- //reg [15:0] clk_count;
-
- /*
- always @(posedge sys_clk or negedge rst_n)
- begin
- if (~rst_n)
- clk_count <= 16'b0;
- else
- if (clk_count==16'd4)
- clk_count<= 0;
- else
- clk_count <= clk_count + 1'b1;
-
- end */// always @ (posedge sys_clk or negedge rst_n)
-
- // assign dynamic_clk = (clk_count==16'd4);
-
-
- reg oled,drive_on;
- reg oled_int;
- reg [15:0] bw_count;
- reg [7:0] ba_reg = 8'b10011001;
- reg reload_ba_reg;
- reg driver_busy;
-
- wire [7:0] BW;
- reg [15:0] BWx10 /* synthesis syn_multstyle = logic */;
- reg [2:0] bit_cnt;
- reg byte_done_int;
- reg txn_start_d;
- /////////////////TXN_Start edge detect/////////////////
-
- always @(posedge sys_clk or negedge rst_n)
- begin
- if (~rst_n || !mobeam_start_stop) begin
- txn_start_d<= 1'b0;
- end
- else
- txn_start_d<=txn_start;
-
- end
- assign txn_start_pos = txn_start & (~txn_start_d);
-
-
-
-
-assign BW =bar_width;
-//assign byte_done_mod= (&bit_cnt) & reload_ba_reg;
-//assign byte_done_mod= (&bit_cnt) && (bw_count==1'b1);
-assign byte_done_mod= (BWx10==16'd4)?(&bit_cnt) && (bw_count==1'b1):byte_done_int;
-assign byte_done = byte_done_mod;
-assign bit_done = reload_ba_reg;
- // assign BWx10 = BW * 10 - 1'b1;
-
- always @(posedge sys_clk or negedge rst_n)
- begin
- if (~rst_n || !mobeam_start_stop) begin
- ba_reg <= 8'd0;
- BWx10<=16'd4;
- byte_done_int<= 1'b0;
- bit_cnt<= 3'd0;
- end
- else begin
- if (BW==0)
- BWx10<= 4;
- else begin
- BWx10 <= BW * 10 - 1'b1;
- // BWX5 <= BW * 5 - 1'b1; //for 25% duty cycle
- // BWX15 <=
- end
-
- //if (txn_start_pos) begin
- if (txn_start && bit_cnt==3'd0) begin
- ba_reg <=barcode_array;
- end
- if (reload_ba_reg) begin
- //ba_reg <= {ba_reg[0],ba_reg[7:1]}; //lsb first
- ba_reg <= {ba_reg[6:0],ba_reg[7]}; //msb first
- if (bit_cnt==3'd7)
- byte_done_int<=1'b1;
- else
- byte_done_int<=1'b0;
-
- if (&bit_cnt) begin
- //byte_done_int<=1'b1;
- bit_cnt<= 3'd0;
- end
- else begin
- // byte_done_int<= 1'b0;
- bit_cnt<= bit_cnt + 1'b1;
- end
-
- end
- else
- byte_done_int<= 1'b0;
- end
- end
-
- always @(posedge sys_clk or negedge rst_n)
- begin
- if (~rst_n || !mobeam_start_stop)
- begin
- oled_int <= 1'b0;
- bw_count <= 16'b0;
- reload_ba_reg <= 1'b0;
- driver_busy<= 1'b0;
-
- end
- else
- if (txn_start) begin
- // driver_busy<= 1'b1;
- if (bw_count == BWx10)
- begin
- //oled<=ba_reg[0]; //lsb_first
- oled_int<=ba_reg[7]; //msb first
- bw_count<=16'b0;
- reload_ba_reg <= 1'b1;
- end
-
- else begin
- oled_int<= oled_int;
- bw_count<= bw_count + 1'b1;
- reload_ba_reg <= 1'b0;
- end
- end
- else
- reload_ba_reg <= 1'b0;
- end // always @ (posedge sys_clk or negedge rst_n)
-
- always @(posedge sys_clk ) begin
- if (~rst_n || !mobeam_start_stop) begin
- oled<=0;
- end else begin
- if(led_polarity)begin
- oled <= oled_int;
- drive_on<=oled_int;
- end else begin
- oled <= ~oled_int;
- drive_on<=~oled_int;
- end
- end
-
- end
-
-endmodule // clk_gen
-
diff --git a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/mobeam_control_fsm_19022014.v b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/mobeam_control_fsm_19022014.v
deleted file mode 100644
index d824cda12..000000000
--- a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/mobeam_control_fsm_19022014.v
+++ /dev/null
@@ -1,1009 +0,0 @@
-//==================================================================
-// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-// ------------------------------------------------------------------
-// Copyright (c) 2014 by Lattice Semiconductor Corporation
-// ALL RIGHTS RESERVED
-// ------------------------------------------------------------------
-//
-// Permission:
-//
-// Lattice SG Pte. Ltd. grants permission to use this code for use
-// in synthesis for any Lattice programmable logic product. Other
-// use of this code, including the selling or duplication of any
-// portion is strictly prohibited.
-
-//
-// Disclaimer:
-//
-// This VHDL or Verilog source code is intended as a design reference
-// which illustrates how these types of functions can be implemented.
-// It is the user's responsibility to verify their design for
-// consistency and functionality through the use of formal
-// verification methods. Lattice provides no warranty
-// regarding the use or functionality of this code.
-//
-// --------------------------------------------------------------------
-//
-// Lattice SG Pte. Ltd.
-// 101 Thomson Road, United Square #07-02
-// Singapore 307591
-//
-//
-// TEL: 1-800-Lattice (USA and Canada)
-// +65-6631-2000 (Singapore)
-// +1-503-268-8001 (other locations)
-//
-// web: http://www.latticesemi.com/
-// email: techsupport@latticesemi.com
-//
-// --------------------------------------------------------------------
-//
-
-
-module mobeam_control_fsm(
- //`ifndef SIM
- input shift_done,
- input bit_done,
- // `endif
- input sys_clk_i,
- input rst_mobeam,
-// input new_data_rd,
-// input data_strobe,
- input start_stop,
-
-// output reg config_reg_done,
-// output reg write_to_bsr_buffer,
-
- //bsr memory signals
- input [7:0] bsr_mem_data,
- output bsr_mem_clk,
- output reg [8:0] bsr_mem_addr,
- output reg bsr_mem_rd_en,
-
- //ba memory signals
- input [15:0] ba_mem_data ,
- output ba_mem_clk,
- output reg [7:0] ba_mem_addr,
- output reg ba_mem_rd_en,
-
- //TO LED DRIVER
- output [7:0] o_byte_data,
- output txn_start,
-// output reg bsr_load_done,
- output reg [7:0] bsr_bw
-);
-
-`define IDLE_BSR 0
-`define LB_READ 1
-`define LB_READ_LATENCY 2
-`define LP_READ 3
-`define LP_READ_LATENCY 4
-`define BL_READ 5
-`define BL_READ_LATENCY 6
-`define NH_READ 7
-`define NH_READ_LATENCY 8
-`define NR_READ 9
-`define NR_READ_LATENCY 10
-
-`define BSR_READ 11
-`define BSR_READ_LATENCY 12
-`define START_HOP 13
-//`define BEAM_START_STOP
-//`define BEAM_START_STOP_LATENCY 10
-
-`define IDLE_STATE 14
-`define READ_WORD 15
-`define READ_BYTE_LATENCY_1 16
-`define DELAY_STATE 17
-`define SHIFT_WORD 18
-
-
-
-// ==============================================================================
-// state assignments & defines
-// ==============================================================================
-parameter BSR_ADDR_WIDTH = 3 ;
-parameter BSR_MEM_DEPTH = 1 << BSR_ADDR_WIDTH ;
-///mobeam reg addresses////////////
-//parameter revision_code_addr=8'hEE; //EE
-parameter rst_mobeam_addr=8'hF1; //ED
-parameter lb_addr=8'hEA; //F0
-parameter lp_addr=8'hEB; //EF
-parameter bl_addr=8'hEC; //E9
-parameter nh_addr=8'hED; //EA
-parameter nr_addr=8'hEE; //EB
-parameter bsr_addr=8'h80;
-parameter ba_addr=8'h00;
-parameter beam_start_stop_addr=8'hF0; //EC
-
-
-
-integer bsr_data_count;
-reg rd_done;
-reg i,i_2;
-
-reg [7:0] o_lb_data;
-reg [7:0] o_lp_data;
-reg [7:0] o_nh_data;
-reg [7:0] o_nr_data;
-reg [7:0] o_bl_data;
-reg [7:0] o_bsr_data;
-reg [4:0] ba_state;
-reg [4:0] bsr_state;
-reg [7:0] bsr_buffer [0:6];
-reg config_reg_done;
-//reg write_to_bsr_buffer;
-
-
-//reg start_stop; //from mobeam reg set
-//wire shift_done; //from led control logic
-
-
-
-
-//////////////////////////BA FSM////////////////////////////////////////////////
-
- assign ba_mem_clk=sys_clk_i;
- reg [7:0] byte_data;
- wire bl_done;
- reg [1:0]check_shift_done_count_d;
-
- always @(posedge sys_clk_i or posedge rst_mobeam) begin
- if(rst_mobeam || !start_stop) begin
- //check_clk_1=0;
- //check_clk_2=0;
- byte_data <= 8'd0;
- check_shift_done_count_d<=0;
- end
- else begin
- check_shift_done_count_d<=check_shift_done_count;
- // if(ba_state!=`IDLE_STATE) begin
-
- if(check_shift_done_count_d==2'b01) begin
- //if(check_clk_1==1) begin
- byte_data<=ba_mem_data[15:8];
- //check_clk_1=0;
- //end
- //else
- //check_clk_1=1;
- end
- else if(check_shift_done_count_d==2'b00) begin
- //if(check_clk_2==1) begin
- byte_data<=ba_mem_data[7:0];
- //check_clk_2=0;
- //end
- //else
- //check_clk_2=1;
- end
- else
- byte_data<=byte_data;
- end
- end
-
-
-
-
- ////*****count shift_done's***************////
-
- reg [1:0] check_shift_done_count;
- reg clk_count_2,clk_count_3;
-
- always @(posedge sys_clk_i or posedge rst_mobeam) begin
- if(rst_mobeam || !start_stop) begin
- clk_count_2<=0;
- clk_count_3<=0;
- check_shift_done_count<=2'b00;
- end
- else begin
- if(/*tx_out_en_high_dtc*/symbol_shift_done)
- check_shift_done_count<=0;
- else if(shift_done) begin
- // if(clk_count_2==1) begin
- // clk_count_2<=0;
- check_shift_done_count<=check_shift_done_count + 1;
- // end
- // else begin
- // check_shift_done_count<=check_shift_done_count;
- // end
- // clk_count_2<=clk_count_2 + 1;
- end
- else if(check_shift_done_count==2'b10) begin
- // if(clk_count_3==1) begin
- check_shift_done_count<=0;
- // clk_count_3<=0;
- // end
- // else begin
- // check_shift_done_count<=check_shift_done_count;
- // end
- // clk_count_3<=clk_count_3+1;
- end
- else
- check_shift_done_count<=check_shift_done_count;
- end
- end
-
- /*
- always @(posedge sys_clk_i or negedge rst_mobeam_n) begin
- if(!rst_mobeam_n) begin
- clk_count_2<=0;
- clk_count_3<=0;
- check_shift_done_count<=2'b00;
- end
- else begin
-
- if(shift_done) begin
- if(clk_count_2==1) begin
- clk_count_2<=0;
- check_shift_done_count<=check_shift_done_count + 1;
- end
- else begin
- check_shift_done_count<=check_shift_done_count;
- end
- clk_count_2<=clk_count_2 + 1;
- end
- else if(check_shift_done_count==2'b10) begin
- if(clk_count_3==1) begin
- check_shift_done_count<=0;
- clk_count_3<=0;
- end
- else begin
- check_shift_done_count<=check_shift_done_count;
- end
- clk_count_3<=clk_count_3+1;
- end
- else
- check_shift_done_count<=check_shift_done_count;
- end
- end
- */
- //assign check_shift_done_count= (!rst_mobeam_n) ? 3'b000 : shift_done ? (check_shift_done_count + 1) : check_shift_done_count;
-
- wire incr_ba_mem_addr;
- reg q_tx_out_en_0,q_tx_out_en_1;
- assign incr_ba_mem_addr=(check_shift_done_count==2'b10) ? 1 : 0;
- //assign bl_done=(bl_byte_count_3==o_bl_data + 1) ? 1 : 0;
- //assign o_byte_data=((bl_byte_count_3 >0) && !bl_done) ? byte_data : 8'bz;
- //assign o_byte_data= ba_mem_rd_en ? (/*(isd_delay_en || ipd_delay_en)*/ !tx_out_en ? 8'bz : byte_data) : 0;
-
- assign o_byte_data= byte_data;
- assign txn_start = q_tx_out_en_1;
-
-
- //assign txn_start = tx_out_en; //orignal
-
- always @(posedge sys_clk_i or posedge rst_mobeam) begin
- if(rst_mobeam || !start_stop) begin
- q_tx_out_en_0<=0;
- q_tx_out_en_1<=0;
- end
- else begin
- q_tx_out_en_0<=tx_out_en;
- q_tx_out_en_1<=q_tx_out_en_0;
- end
- end
- wire tx_out_en_high_dtc;
-
- assign tx_out_en_high_dtc= ~q_tx_out_en_0 && tx_out_en;
-
-//////////////BA FSM/////////////////////////////////////////////
- always @(posedge sys_clk_i or posedge rst_mobeam) begin
- if(rst_mobeam) begin
- ba_mem_addr<=0;
- ba_mem_rd_en<=0;
- ba_state<=`IDLE_STATE;
- end
- else begin
- case(ba_state)
- `IDLE_STATE: begin
- ba_mem_addr<=0;
- ba_mem_rd_en<=0;
- if(/*start_stop*/ config_reg_done)
- ba_state<=`READ_WORD;
- else
- ba_state<=`IDLE_STATE;
- end
-
- `READ_WORD:begin
- ba_mem_rd_en<=1;
- if(!start_stop)
- ba_state<=`IDLE_STATE;
- else if(symbol_shift_done) //make address=0 when #shift_done's == o_bl_data
- ba_mem_addr<=0;
- else if(!tx_out_en)
- ba_state<=`DELAY_STATE;
- else if(incr_ba_mem_addr) begin
- ba_mem_addr<=ba_mem_addr + 1;
- ba_state<=`READ_BYTE_LATENCY_1;
- end
- else begin
- ba_mem_addr<=ba_mem_addr;
- ba_state<=`READ_WORD;
- end
- end
-
- `READ_BYTE_LATENCY_1:begin
- if(!start_stop)
- ba_state<=`IDLE_STATE;
- else
- ba_state<=`READ_WORD;
- end
-
- `DELAY_STATE:begin
- if(!start_stop)
- ba_state<=`IDLE_STATE;
- else begin
- ba_mem_addr<=ba_mem_addr;
- if(tx_out_en)
- ba_state<=`READ_WORD;
- else
- ba_state<=`DELAY_STATE;
- end
- end
-
- endcase
- end //else begin
- end //else always
-/////////////////////////////////////////////////////////////////
- reg start_stop_count;
-
- always @(posedge sys_clk_i or posedge rst_mobeam) begin
- if(rst_mobeam) begin
- start_stop_count=0;
- end
- else begin
- if(start_stop)
- start_stop_count=1;
- end
- end
-
-
-//////////////////BSR FSM///////////////////////////////////////
-
-
-
-assign bsr_mem_clk=sys_clk_i;
-reg state_count;
-reg init_addr_read_done;
-reg [8:0] prev_mem_rd_addr;
-reg [8:0] next_mem_rd_addr;
-
- always @(posedge sys_clk_i or posedge rst_mobeam) begin
- if(rst_mobeam) begin
- bsr_state<=`IDLE_BSR;
- i<=0;
- i_2<=0;
- bsr_data_count<=0;
- // write_to_bsr_buffer<=0;
- state_count<=0;
- config_reg_done<=0;
- next_mem_rd_addr<=0;
- bsr_mem_addr<=0;
- prev_mem_rd_addr<=0;
- bsr_mem_rd_en<=1'b1;
- // bsr_load_done<=0;
- init_addr_read_done<=0;
- rd_done<=1'b0;
- o_lb_data<=0;
- o_lp_data<=0;
- o_nh_data<=0;
- o_nr_data<=0;
- o_bl_data<=0;
- o_bsr_data<=0;
- end
- else begin
-
- case(bsr_state)
- `IDLE_BSR:begin
- i<=0;
- i_2<=0;
- bsr_data_count<=0;
- // write_to_bsr_buffer<=0;
- state_count<=0;
- config_reg_done<=0;
- next_mem_rd_addr<=0;
- bsr_mem_addr<=0;
- prev_mem_rd_addr<=0;
- bsr_mem_rd_en<=1'b1;
- // bsr_load_done<=0;
- init_addr_read_done<=0;
- rd_done<=1'b0;
- if (start_stop==1)
- bsr_state<=`LB_READ;
- else
- bsr_state<=`IDLE_BSR;
- end
-
-
- `LB_READ:begin
- bsr_mem_addr<=lb_addr;
- bsr_mem_rd_en<=1'b1;
- bsr_state<=`LB_READ_LATENCY;
- end
-
- `LB_READ_LATENCY:begin
- state_count<=state_count + 1;
- if(state_count==1) begin
- o_lb_data<=bsr_mem_data;
- state_count<=0;
- bsr_state<=`LP_READ;
- end
- else
- bsr_state<=`LB_READ_LATENCY;
- end
-
- `LP_READ:begin
- bsr_mem_addr<=lp_addr;
- bsr_mem_rd_en<=1'b1;
- bsr_state<=`LP_READ_LATENCY;
- end
-
- `LP_READ_LATENCY:begin
- state_count<=state_count + 1;
- if(state_count==1) begin
- o_lp_data<=bsr_mem_data;
- state_count<=0;
- bsr_state<=`BL_READ;
- end
- else
- bsr_state<=`LP_READ_LATENCY;
- end
-
- `BL_READ:begin
- bsr_mem_addr<=bl_addr;
- bsr_mem_rd_en<=1'b1;
- bsr_state<=`BL_READ_LATENCY;
-
- end
-
- `BL_READ_LATENCY:begin
- state_count<=state_count + 1;
- if(state_count==1) begin
- o_bl_data<=bsr_mem_data;
- state_count<=0;
- bsr_state<=`NH_READ;
- end
- else
- bsr_state<=`BL_READ_LATENCY;
- end
-
- `NH_READ:begin
- bsr_mem_addr<=nh_addr;
- bsr_mem_rd_en<=1'b1;
- bsr_state<=`NH_READ_LATENCY;
- end
-
- `NH_READ_LATENCY:begin
- state_count<=state_count + 1;
- if(state_count==1) begin
- o_nh_data<=bsr_mem_data;
- state_count<=0;
- bsr_state<=`NR_READ;
- end
- else
- bsr_state<=`NH_READ_LATENCY;
- end
-
- `NR_READ:begin
- bsr_mem_addr<=nr_addr;
- bsr_mem_rd_en<=1'b1;
- rd_done<=1'b1;
- bsr_state<=`NR_READ_LATENCY;
- end
-
- `NR_READ_LATENCY:begin
- state_count<=state_count + 1;
- if(state_count==1) begin
- o_nr_data<=bsr_mem_data;
- state_count<=0;
- bsr_state<=`BSR_READ;
- end
- else
- bsr_state<=`NR_READ_LATENCY;
- end
-
-
- `BSR_READ:begin
- if (i==0) begin
- i<=1'b1;
- bsr_data_count<=0;
-
- if(init_addr_read_done==0 || nh_hop_shift_done_2)
- bsr_mem_addr<=bsr_addr;
- else if(hop_shift_done_3) begin //if shift_count==np*ns then next 8 bytes else
- //config_reg_done<=0;
- bsr_mem_addr<=next_mem_rd_addr+1;
- end
- else
- bsr_mem_addr<=prev_mem_rd_addr;
-
- bsr_mem_rd_en<=1'b1;
- bsr_state<=`BSR_READ_LATENCY;
- end
- else begin
- bsr_mem_addr<=bsr_mem_addr+1;
- bsr_data_count<=bsr_data_count+1;
- if (bsr_data_count==6) begin //read all 8 bytes of bsr data,increament hop_count
- // bsr_data_count<=0;
- next_mem_rd_addr<=bsr_mem_addr;
- // write_to_bsr_buffer<=0;
- // bsr_load_done<=1;
- config_reg_done<=1;
- //bsr_state<=`BEAM_START_STOP;
- bsr_state<=`START_HOP;
- end
- else begin
- config_reg_done<=config_reg_done;
- bsr_state<=`BSR_READ_LATENCY;
- end
- end
- end
-
- `BSR_READ_LATENCY:begin
- if(i_2==1'b0) begin /*store first address in temp register*/
- i_2<=1'b1;
- prev_mem_rd_addr<=bsr_mem_addr;
- end
- state_count<=state_count + 1;
- // write_to_bsr_buffer<=1;
- if(state_count==1) begin
- o_bsr_data<=bsr_mem_data;
- bsr_buffer[bsr_data_count]<=bsr_mem_data;
- state_count<=0;
- bsr_state<=`BSR_READ;
- end
- else begin
- bsr_state<=`BSR_READ_LATENCY;
- // write_to_bsr_buffer<=0;
- end
- end
-
- `START_HOP: begin
- i<=1'b0;
- i_2<=1'b0;
- // bsr_load_done<=0;
- init_addr_read_done<=1;
- if(!start_stop && start_stop_count)
- bsr_state<=`IDLE_BSR;
- else if(hop_shift_done)
- bsr_state<=`BSR_READ;
- else
- bsr_state<=`START_HOP;
- end
-
-
- // `BEAM_START_STOP: begin
- // i<=1'b0;
- // i_2<=1'b0;
- // init_addr_read_done<=1;
- // bsr_load_done<=0;
- // rd_done<=1'b0;
- // bsr_mem_addr<=beam_start_stop_addr;
- // bsr_mem_rd_en<=1'b1;
- // if(hop_shift_done/*symbol_shift_done*/)
- // bsr_state<=`BSR_READ;
- // else
- // bsr_state<=`BEAM_START_STOP_LATENCY;
- // end
-
- // `BEAM_START_STOP_LATENCY:begin
- // state_count<=state_count + 1;
- // if(state_count==1) begin
- // state_count<=0;
- // if (bsr_mem_data==8'b00000001) begin
- // start_stop<=1'b1;
- // if(hop_shift_done/*symbol_shift_done*/)
- // bsr_state<=`BSR_READ;
- // else
- // bsr_state<=`BEAM_START_STOP;
- // end
- // else begin
- // start_stop<=1'b0;
- // bsr_state<=`IDLE_BSR;
- // end
- // end
- // else
- // bsr_state<=`BEAM_START_STOP_LATENCY;
- // end
-
- endcase
-
- end
- end
-
- /////*********edge detection for config_reg_done***********////////////
- reg q_config_reg_done;
- always @(posedge sys_clk_i or posedge rst_mobeam) begin
- if(rst_mobeam)
- q_config_reg_done<=0;
- else
- q_config_reg_done<=config_reg_done;
- end
-
- assign config_reg_done_pos_dtc= config_reg_done && (~q_config_reg_done);
-
-
-////**************LOGIC TO FIND PACKET AND SYMBOL COUNT*************/////////
- reg [7:0] packet_count;
- reg [3:0] hop_count;
- reg [7:0] symbol_count;
- reg [7:0] shift_done_count;
- reg symbol_shift_done,symbol_shift_done_2,symbol_shift_done_3;
- reg packet_shift_done;
- reg hop_shift_done,hop_shift_done_2,hop_shift_done_3;
- reg clk_count,clk_count_4;
- reg nh_hop_shift_done,nh_hop_shift_done_2,nh_hop_shift_done_3;
-
- assign nh_hop_shift_done_led=nh_hop_shift_done_3;
-
-
- always @(posedge sys_clk_i or posedge rst_mobeam) begin
- if(rst_mobeam) begin
- packet_count=0;
- hop_count=0;
- hop_shift_done=0;
- shift_done_count=0;
- symbol_count=0;
- clk_count<=0;
- clk_count_4<=0;
- hop_shift_done_2<=0;
- hop_shift_done_3<=0;
- nh_hop_shift_done<=0;
- nh_hop_shift_done_2<=0;
- nh_hop_shift_done_3<=0;
- symbol_shift_done<=0;
- symbol_shift_done_2<=0;
- symbol_shift_done_3<=0;
- packet_shift_done=0;
- end
- else begin
- if(start_stop) begin
- hop_shift_done=0;
- nh_hop_shift_done<=0;
- symbol_shift_done<=0;
- packet_shift_done=0;
- if(shift_done) begin
- //clk_count<=clk_count+1;
- //if(clk_count==1'b1) begin //orignal
- //clk_count<=0;
- if(shift_done_count==(o_bl_data-1)) begin //bl check
- shift_done_count=0;
- symbol_shift_done<=1;
- if(symbol_count==(bsr_ns-1)) begin //symbol_check
- symbol_count=0;
- packet_shift_done=1;
- if(packet_count==(bsr_np-1)) begin //packet check
- packet_count=0;
- hop_shift_done=1;
- if(hop_count==(o_nh_data-1)) begin //hop_check
- hop_count=0;
- nh_hop_shift_done<=1;
- end
- else begin
- hop_count=hop_count + 1; //hop_check
- end
- end
- else begin //packet check
- packet_count=packet_count+1;
- hop_shift_done=0;
- end
- end
- else begin
- symbol_count=symbol_count+1;
- end
- end
- else
- shift_done_count=shift_done_count+1; //bl check
- end
- else
- //shift_done_count=shift_done_count+1; //orignal
- shift_done_count=shift_done_count;
- //end //orignal
-
- nh_hop_shift_done_2<=nh_hop_shift_done;
- nh_hop_shift_done_3<=nh_hop_shift_done_2;
- hop_shift_done_2<=hop_shift_done;
- hop_shift_done_3<=hop_shift_done_2;
- symbol_shift_done_2<=symbol_shift_done;
- symbol_shift_done_3<=symbol_shift_done_2;
- end
- else begin
- packet_count=0;
- hop_count=0;
- hop_shift_done=0;
- shift_done_count=0;
- symbol_count=0;
- clk_count<=0;
- clk_count_4<=0;
- hop_shift_done_2<=0;
- hop_shift_done_3<=0;
- nh_hop_shift_done<=0;
- nh_hop_shift_done_2<=0;
- nh_hop_shift_done_3<=0;
- symbol_shift_done<=0;
- symbol_shift_done_2<=0;
- symbol_shift_done_3<=0;
- packet_shift_done=0;
- end
- end
-end
- /*
-
- always @(posedge sys_clk_i or negedge rst_mobeam_n) begin
- if(!rst_mobeam_n) begin
- packet_count=0;
- hop_count=0;
- hop_shift_done=0;
- shift_done_count=0;
- clk_count<=0;
- nh_hop_shift_done=0;
- end
- else begin
- if(start_stop) begin
- hop_shift_done=0;
- nh_hop_shift_done=0;
- if(shift_done) begin
- clk_count<=clk_count+1;
- if(clk_count==1'b1) begin
- clk_count<=0;
- if(shift_done_count==(bsr_ns-1)) begin
- shift_done_count=0;
- if(packet_count==(bsr_np-1)) begin
- packet_count=0;
- if(hop_count==(o_nh_data-1)) begin
- hop_count=0;
- nh_hop_shift_done=1;
- // hop_shift_done=1;
- end
- else begin
- hop_shift_done=1;
- hop_count=hop_count + 1;
- end
- end
- else begin
- packet_count=packet_count+1;
- hop_shift_done=0;
- end
- end
- else
- shift_done_count=shift_done_count+1;
- end
- end
- else
- shift_done_count=shift_done_count;
- end
- else begin
- shift_done_count=0;
- packet_count=0;
- hop_count=0;
- hop_shift_done=0;
- end
- end
-end
-*/
-/////////*******BSR CONTROL REGSITER DATA******************////////
-
-wire [7:0] bsr_bw_int; //bar width
-wire [7:0] bsr_ns; //number of symbols
-wire [15:0] bsr_isd; //inter symbol distance
-wire [7:0] bsr_np; //number of packets
-wire [15:0] bsr_ipd; //inter packet distance
-//wire [55:0] control_reg;
-
-//assign bsr_bw = bsr_bw_int; //orignal
-
-always @(posedge sys_clk_i or posedge rst_mobeam) begin
- if(rst_mobeam || !start_stop) begin
- bsr_bw<= 0;
- end
-else
- if (hop_after_txn_neg || config_reg_done_pos_dtc) //added "|| config_reg_done_pos_dtc" on 13/feb/2014
- bsr_bw <= bsr_bw_int;
- //else
- //bsr_bw <= bsr_bw;
- end
-
-
-
-
-//assign bsr_bw = (bsr_data_count==31'd7) ? (hop_after_txn_neg ? bsr_bw_int : bsr_bw) : 0 ;
-
-
-assign bsr_bw_int=(bsr_data_count==31'd7) ? {bsr_buffer[0][7:0]} : 0;
-assign bsr_ns=(bsr_data_count==31'd7) ? bsr_buffer[1][7:0] : 0;
-assign bsr_isd=(bsr_data_count==31'd7) ?{bsr_buffer[3][7:0],bsr_buffer[2][7:0]} : 0;
-assign bsr_np=(bsr_data_count==31'd7) ? bsr_buffer[4][7:0] : 0;
-assign bsr_ipd=(bsr_data_count==31'd7) ? {bsr_buffer[6][7:0],bsr_buffer[5][7:0]}: 0;
-
-//assign control_reg=!rst_mobeam ? 56'bz : bsr_load_done ? {bsr_ipd,bsr_np,bsr_isd,bsr_ns,bsr_bw}:control_reg;
-
-//assign o_ba_mem_data=start_stop ? ba_mem_data : 16'bz;
-//assign o_ba_mem_data=(ba_state==`SHIFT_WORD) ? ba_mem_data : 16'bz;
-
-/************************************************************************/
-
-
-
-
-/////***************FSM DECODE********************//////////////
- /*AUTOASCIIENUM("bsr_state" "state_ASCII")*/
- // Beginning of automatic ASCII enum decoding
- reg [111:0] state_ASCII; // Decode of bsr_state
- always @(bsr_state) begin
- case ({bsr_state})
- `IDLE_BSR : state_ASCII = "IDLE_BSR ";
- `NH_READ : state_ASCII = "NH_READ";
- `NH_READ_LATENCY: state_ASCII = "NH_READ_LATENCY ";
- `NR_READ : state_ASCII = "NR_READ ";
- `NR_READ_LATENCY: state_ASCII = "NR_READ_LATENCY ";
- `BL_READ : state_ASCII = "BL_READ ";
- `BL_READ_LATENCY: state_ASCII = "BL_READ_LATENCY ";
- `BSR_READ : state_ASCII = "BSR_READ ";
- `BSR_READ_LATENCY: state_ASCII = "BSR_READ_LATENCY ";
- `START_HOP : state_ASCII = "START_HOP ";
- `LB_READ : state_ASCII = "LB_READ ";
- `LB_READ_LATENCY: state_ASCII = "LB_READ_LATENCY ";
- `LP_READ : state_ASCII = "LP_READ ";
- `LP_READ_LATENCY: state_ASCII = "LP_READ_LATENCY ";
-
- //`BEAM_START_STOP : state_ASCII = "BEAM_START_STOP ";
- //`BEAM_START_STOP_LATENCY: state_ASCII = "BEAM_START_STOP_LATENCY ";
- default: state_ASCII = "%Error ";
- endcase
- end
- // End of automatics
-
- /*AUTOASCIIENUM("ba_state" "state_ASCII")*/
- // Beginning of automatic ASCII enum decoding
- reg [111:0] ba_state_ASCII; // Decode of ba_state
- always @(ba_state) begin
- case ({ba_state})
- `IDLE_STATE : ba_state_ASCII = "IDLE_STATE ";
- `READ_WORD : ba_state_ASCII = "READ_WORD";
- `READ_BYTE_LATENCY_1: ba_state_ASCII = "READ_BYTE_LATENCY_1 ";
- `DELAY_STATE : ba_state_ASCII = "DELAY_STATE ";
-
- `SHIFT_WORD : ba_state_ASCII = "SHIFT_WORD ";
- default: ba_state_ASCII = "%Error ";
- endcase
- end
- // End of automatics
-////////////////********************************////////////////////
- /*
-wire isd_delay_en;
-wire ipd_delay_en;
-wire low_isd_delay_en_dtc;
-wire tx_out_en;
-
-
-reg q1_isd_delay_en,q2_isd_delay_en;
-
-
-always @(posedge sys_clk_i or posedge rst_mobeam) begin
- if(rst_mobeam) begin
- q1_isd_delay_en<=0;
- q2_isd_delay_en<=0;
- end
- else begin
- q1_isd_delay_en<=isd_delay_en;
- q2_isd_delay_en<=q1_isd_delay_en;
- end
- end
- */
-// assign low_isd_delay_en_dtc= q1_isd_delay_en && ~isd_delay_en ;///*&& q2_isd_delay_en*/;
-
-wire isd_delay_en;
-wire ipd_delay_en;
-wire low_isd_delay_en_dtc;
-
-
-//assign tx_out_en= ba_mem_rd_en ? ((isd_delay_en || ipd_delay_en) ? 0 : 1) : 0;
-
-//assign dummy_tx_out_en= ba_mem_rd_en ? ( (isd_delay_en && ipd_delay_en) ? (ipd_delay_en ? 1 : 0) : (isd_delay_en ? 1 : 0)) : 0 ;
-
-//assign dummy_tx_out_en= ba_mem_rd_en ? (isd_delay_en_rise_dtc ? ((isd_delay_en_rise_dtc && ipd_delay_en_rise_dtc) ? (ipd_delay_en ? 1 : 0) : ipd_delay_en) : (isd_delay_en ? 1 : 0)) : 0 ; //(isd_delay_en ? 1 : 0)) : 0 ;
-
-reg q1_isd_delay_en,q1_ipd_delay_en;
-
-always @(posedge sys_clk_i or posedge rst_mobeam) begin
- if(rst_mobeam || !start_stop) begin
- q1_isd_delay_en<=0;
- q1_ipd_delay_en<=0;
- end
- else begin
- q1_isd_delay_en<=isd_delay_en;
- q1_ipd_delay_en<=ipd_delay_en;
- end
-end
-
-reg tx_out_en;
-
-
-always @(posedge sys_clk_i or posedge rst_mobeam) begin
- if(rst_mobeam || !start_stop) begin
- tx_out_en<=0;
- end
-else begin
- if(ba_mem_rd_en) begin
- if(isd_delay_en_rise_dtc && ipd_delay_en_rise_dtc)
- tx_out_en<=0;
- else if(isd_delay_en_rise_dtc)
- tx_out_en<=0;
- else if(isd_delay_en_fall_dtc && ipd_delay_en) //
- tx_out_en<=0;
- else if(ipd_delay_en_fall_dtc)
- tx_out_en<=1;
- else if(!isd_delay_en && !ipd_delay_en) //
- tx_out_en<=1;
- else
- tx_out_en<=tx_out_en;
- end
- else
- tx_out_en<=0;
- end
-end
-
-assign isd_delay_en_rise_dtc=~q1_isd_delay_en && isd_delay_en;
-assign ipd_delay_en_rise_dtc=~q1_ipd_delay_en && ipd_delay_en;
-assign isd_delay_en_fall_dtc=q1_isd_delay_en && ~isd_delay_en;
-assign ipd_delay_en_fall_dtc=q1_ipd_delay_en && ~ipd_delay_en;
-assign low_isd_delay_en_dtc= q1_isd_delay_en && ~isd_delay_en ;///*&& q2_isd_delay_en*/;
-
-
-reg hop_after_txn,q_hop_after_txn;
-
-always @(posedge sys_clk_i or posedge rst_mobeam) begin
- if(rst_mobeam || !start_stop) begin
- hop_after_txn<=0;
- end
- else begin
- if(hop_shift_done)
- hop_after_txn<=1;
- else if(tx_out_en && bit_done)
- hop_after_txn<=0;
- else
- hop_after_txn<=hop_after_txn;
- end
-end
-
-always @(posedge sys_clk_i or posedge rst_mobeam) begin
- if(rst_mobeam || !start_stop) begin
- q_hop_after_txn<=0;
- end
- else
- q_hop_after_txn<=hop_after_txn;
-end
-
- assign hop_after_txn_neg= (~hop_after_txn) & q_hop_after_txn;
-
-
-delay_gen_ihd_ipd_isd mobeam_delay_gen_inst(
- .clk(sys_clk_i),
- .rst(rst_mobeam),
- .isd_val(bsr_isd),
- .ipd_val(bsr_ipd),
- .start_stop(start_stop),
- .config_reg_done(config_reg_done),
- .hop_shift_done(hop_shift_done),
- .packet_shift_done(packet_shift_done),
- .symbol_shift_done(symbol_shift_done),
- .isd_delay_en(isd_delay_en),
- .ipd_delay_en(ipd_delay_en)
- ) ;
-
- /*
- `ifdef SIM
- reg shift_done;
- initial begin
- shift_done=0;
- #160000
- repeat(1000) begin
- #40000
- shift_done=1;
- #50
- shift_done=0;
- end
-
- end
- `endif
- */
-endmodule
\ No newline at end of file
diff --git a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/mobeam_delay_gen.v b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/mobeam_delay_gen.v
deleted file mode 100644
index 5100e5fe9..000000000
--- a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/mobeam_delay_gen.v
+++ /dev/null
@@ -1,160 +0,0 @@
-//==================================================================
-// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-// ------------------------------------------------------------------
-// Copyright (c) 2014 by Lattice Semiconductor Corporation
-// ALL RIGHTS RESERVED
-// ------------------------------------------------------------------
-//
-// Permission:
-//
-// Lattice SG Pte. Ltd. grants permission to use this code for use
-// in synthesis for any Lattice programmable logic product. Other
-// use of this code, including the selling or duplication of any
-// portion is strictly prohibited.
-
-//
-// Disclaimer:
-//
-// This VHDL or Verilog source code is intended as a design reference
-// which illustrates how these types of functions can be implemented.
-// It is the user's responsibility to verify their design for
-// consistency and functionality through the use of formal
-// verification methods. Lattice provides no warranty
-// regarding the use or functionality of this code.
-//
-// --------------------------------------------------------------------
-//
-// Lattice SG Pte. Ltd.
-// 101 Thomson Road, United Square #07-02
-// Singapore 307591
-//
-//
-// TEL: 1-800-Lattice (USA and Canada)
-// +65-6631-2000 (Singapore)
-// +1-503-268-8001 (other locations)
-//
-// web: http://www.latticesemi.com/
-// email: techsupport@latticesemi.com
-//
-// --------------------------------------------------------------------
-//
-
-
-module mobeam_delay_gen(
- input clk,
- input rst_n,
- input [15:0] isd_val,
- input [15:0] ipd_val,
- input config_reg_done,
- input symbol_shift_done,
- input packet_shift_done,
- output reg isd_delay_en,
- output reg ipd_delay_en
-);
-
-reg [15:0] isd_val_temp;
-reg [15:0] ipd_val_temp;
-reg [15:0] isd_count;
-reg [15:0] ipd_count;
-wire [15:0] max_count,max_count_pkt;
-reg clk_count,clk_count_pkt;
-reg count_done,count_done_pkt;
-
-parameter const=10;
-assign max_count=isd_val_temp * const;
-assign max_count_pkt=ipd_val_temp * const;
-
-wire count_enable,count_enable_pkt;
-//wire config_done;
-//assign config_done= !rst_n ? 0 : config_reg_done ? 1 : config_done;
-assign count_enable= !rst_n ? 0 : count_done ? 0 : symbol_shift_done ? 1 : count_enable;
-assign count_enable_pkt= !rst_n ? 0 : count_done_pkt ? 0 : packet_shift_done ? 1 : count_enable_pkt;
-
-//assign isd_delay_en=symbol_shift_done ? 1 : (isd_count==max_count-1) :
-
-///////////////////////symbol////////////////////////////////////
-always @(posedge clk or negedge rst_n) begin
- if(!rst_n) begin
- isd_count<=0;
- count_done<=0;
- end
- else begin
- count_done<=0;
- if(count_enable) begin
- if(isd_count==max_count-1) begin
- isd_count<=0;
- count_done<=1;
- isd_delay_en<=0;
- end
- else begin
- isd_delay_en<=1;
- isd_count<=isd_count+1;
- end
- end
- else begin
- isd_delay_en<=0;
- isd_count<=0;
- end
- end
-end
-
-always @(posedge clk or negedge rst_n) begin
- if(!rst_n) begin
- isd_val_temp<=0;
- clk_count<=0;
- end
- else begin
- if(clk_count)
- isd_val_temp<=isd_val_temp;
- else if(config_reg_done) begin
- clk_count<=clk_count+1;
- isd_val_temp<=isd_val;
- end
- else
- isd_val_temp<=isd_val_temp;
- end
-end
-///////////////packet//////////////////////
-always @(posedge clk or negedge rst_n) begin
- if(!rst_n) begin
- ipd_count<=0;
- count_done_pkt<=0;
- end
- else begin
- count_done_pkt<=0;
- if(count_enable_pkt) begin
- if(ipd_count==max_count_pkt-1) begin
- ipd_count<=0;
- count_done_pkt<=1;
- ipd_delay_en<=0;
- end
- else begin
- ipd_delay_en<=1;
- ipd_count<=ipd_count+1;
- end
- end
- else begin
- ipd_delay_en<=0;
- ipd_count<=0;
- end
- end
-end
-
-always @(posedge clk or negedge rst_n) begin
- if(!rst_n) begin
- ipd_val_temp<=0;
- clk_count_pkt<=0;
- end
- else begin
- if(clk_count_pkt)
- ipd_val_temp<=ipd_val_temp;
- else if(config_reg_done) begin
- clk_count_pkt<=clk_count_pkt+1;
- ipd_val_temp<=ipd_val;
- end
- else
- ipd_val_temp<=ipd_val_temp;
- end
-end
-
-endmodule
diff --git a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/mobeam_i2c_reg_interface_19022014.v b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/mobeam_i2c_reg_interface_19022014.v
deleted file mode 100644
index c8d1494e8..000000000
--- a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/mobeam_i2c_reg_interface_19022014.v
+++ /dev/null
@@ -1,377 +0,0 @@
-//==================================================================
-// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-// ------------------------------------------------------------------
-// Copyright (c) 2014 by Lattice Semiconductor Corporation
-// ALL RIGHTS RESERVED
-// ------------------------------------------------------------------
-//
-// Permission:
-//
-// Lattice SG Pte. Ltd. grants permission to use this code for use
-// in synthesis for any Lattice programmable logic product. Other
-// use of this code, including the selling or duplication of any
-// portion is strictly prohibited.
-
-//
-// Disclaimer:
-//
-// This VHDL or Verilog source code is intended as a design reference
-// which illustrates how these types of functions can be implemented.
-// It is the user's responsibility to verify their design for
-// consistency and functionality through the use of formal
-// verification methods. Lattice provides no warranty
-// regarding the use or functionality of this code.
-//
-// --------------------------------------------------------------------
-//
-// Lattice SG Pte. Ltd.
-// 101 Thomson Road, United Square #07-02
-// Singapore 307591
-//
-//
-// TEL: 1-800-Lattice (USA and Canada)
-// +65-6631-2000 (Singapore)
-// +1-503-268-8001 (other locations)
-//
-// web: http://www.latticesemi.com/
-// email: techsupport@latticesemi.com
-//
-// --------------------------------------------------------------------
-//
-
-
-module mobeam_i2c_reg_interface(
- rst_i,
- clk_i,
- //i2c slave interface signals///
- i2c_master_to_slave_data_i,
- i2c_slave_to_master_data_o,
- i2c_slave_data_address_i,
- wr_en_i,
- rd_en_i,
- i2c_start_i,
- //MoBeam control logic interface//
- rd_revision_code,
- rst_mobeam,
- mobeam_start_stop,
- led_polarity,
- o_ba_mem_data,
- i_ba_mem_addr,
- i_ba_mem_rd_en,
- i_ba_mem_rd_clk,
- o_bsr_mem_data,
- i_bsr_mem_addr,
- i_bsr_mem_rd_en,
- i_bsr_mem_rd_clk
- // i_config_reg_done,
- // o_new_data_rd,
- // o_data_strobe
- );
-//i2c slave interface signals///
-input [7:0] i2c_master_to_slave_data_i;
-output reg [7:0]i2c_slave_to_master_data_o;
-input [7:0] i2c_slave_data_address_i;
-input wr_en_i;
-input rd_en_i;
-input i2c_start_i;
-input rst_i;
-input clk_i;
-//mobeam control logic interface//
-output [15:0] o_ba_mem_data;
-input [7:0] i_ba_mem_addr;
-input i_ba_mem_rd_en;
-input i_ba_mem_rd_clk;
-output reg rd_revision_code=0;
-output reg rst_mobeam=0;
-//input[7:0] i_revision_code_data;
-//input rd_revision_code;
-output [7:0] o_bsr_mem_data;
-//output reg [15:0] mem_data_buf16;
-input [8:0] i_bsr_mem_addr;
-input i_bsr_mem_rd_en;
-input i_bsr_mem_rd_clk;
-output reg mobeam_start_stop=1'b0;
-output reg led_polarity=1'b0;
-//output reg o_new_data_rd=1'b0;
-//output reg o_data_strobe=1'b0;
-//input i_config_reg_done;
-
-
-
-
-
-
-
-
-//////////////wire & reg declarations//////////////////
-wire wr_en;
-wire rd_en;
-reg d1_wr_en_i;
-reg d2_wr_en_i;
-reg d1_rd_en_i;
-reg d2_rd_en_i;
-
-parameter revision_code=8'hF1;
-
-
-
-
-/////////////////////BSR and CONFIG data memory//////////////
-
-SB_RAM512x8 ram512x8_inst
-(
- .RDATA(o_bsr_mem_data),// EBR512x8_data
- .RADDR(i_bsr_mem_addr),// EBR512x8_addr
- .RCLK(i_bsr_mem_rd_clk),
- .RCLKE(i_bsr_mem_rd_en),
- .RE(i_bsr_mem_rd_en),// EBR512x8_re
- .WADDR({1'b0,bsr_mem_addr_in}),
- .WCLK(clk_i),
- .WCLKE(1'b1),///*bsr_wr_en/*wr_en*/),
- .WDATA(i2c_master_to_slave_data_i),
- .WE(bsr_wr_en) ////*bsr_wr_en/*wr_en*/)
-);
-
-defparam ram512x8_inst.INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-defparam ram512x8_inst.INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-defparam ram512x8_inst.INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-defparam ram512x8_inst.INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-defparam ram512x8_inst.INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-defparam ram512x8_inst.INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-//ICE Technology Library 66
-//Lattice Semiconductor Corporation Confidential
-defparam ram512x8_inst.INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-defparam ram512x8_inst.INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-defparam ram512x8_inst.INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-defparam ram512x8_inst.INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-defparam ram512x8_inst.INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-defparam ram512x8_inst.INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-defparam ram512x8_inst.INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-defparam ram512x8_inst.INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-defparam ram512x8_inst.INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-defparam ram512x8_inst.INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-
-
-///////////////////////BA i.e. beamable data memory//////////////
-SB_RAM256x16 ram256x16_inst (
-.RDATA(o_ba_mem_data),
-.RADDR(i_ba_mem_addr),
-.RCLK(i_ba_mem_rd_clk),
-.RCLKE(i_ba_mem_rd_en),
-.RE(i_ba_mem_rd_en),
-.WADDR(ba_mem_addr_in_delayed_1),
-.WCLK(clk_i),
-.WCLKE(1'b1),///*ba_wr_en/*wr_en*/),
-.WDATA(ba_mem_data_buffer),
-.WE(ba_wr_en_delayed),///*wr_en*/),
-.MASK(16'd0)
-);
-defparam ram256x16_inst.INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-defparam ram256x16_inst.INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-defparam ram256x16_inst.INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-defparam ram256x16_inst.INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-defparam ram256x16_inst.INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-defparam ram256x16_inst.INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-defparam ram256x16_inst.INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-defparam ram256x16_inst.INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-defparam ram256x16_inst.INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-defparam ram256x16_inst.INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-defparam ram256x16_inst.INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-defparam ram256x16_inst.INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-defparam ram256x16_inst.INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-defparam ram256x16_inst.INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-defparam ram256x16_inst.INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-defparam ram256x16_inst.INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-
-
-// Write valid pulse
-always @(posedge clk_i or posedge rst_i) begin
- if (rst_i) begin
- d1_wr_en_i <= 0;
- d2_wr_en_i <= 0;
- end else begin
- d1_wr_en_i <= wr_en_i;
- d2_wr_en_i <= d1_wr_en_i;
- end
-end
-
-assign wr_en = d2_wr_en_i && ~d1_wr_en_i;
-
-// Read enable pulse
-always @(posedge clk_i or posedge rst_i) begin
- if (rst_i) begin
- d1_rd_en_i <= 0;
- d2_rd_en_i <= 0;
- end else begin
- d1_rd_en_i <= rd_en_i;
- d2_rd_en_i <= d1_rd_en_i;
- end
-end
-
-
-assign rd_en = ~d2_rd_en_i && d1_rd_en_i;
-
-reg [7:0] bsr_mem_addr_in;
-
-reg [7:0] ba_mem_addr_in;
-reg ba_wr_en;
-
-
-always @(posedge clk_i or posedge rst_i) begin
- if (rst_i) begin
- bsr_mem_addr_in <= 9'd0;
-
- end
-else
- if (i2c_start_i)
- bsr_mem_addr_in <= i2c_slave_data_address_i;
-
- else if (i2c_slave_data_address_i == 8'h80) begin
- if (wr_en) begin
- bsr_mem_addr_in <=bsr_mem_addr_in + 1'b1;
-
- end
-
- end
-end
-
-assign bsr_wr_en = (i2c_slave_data_address_i == 8'h00)?1'b0:wr_en;
-
-//MOBEAM START-STOP
-always @(posedge clk_i or posedge rst_i) begin
- if (rst_i) begin
- mobeam_start_stop<=1'b0;
-
- end
-else
- if (i2c_slave_data_address_i == 8'hF0) //8'hEC
- if (wr_en & (i2c_master_to_slave_data_i==8'b00000001))begin
- mobeam_start_stop<=1'b1;
- end
- else if(wr_en & (i2c_master_to_slave_data_i==8'b00000000))begin
- mobeam_start_stop<=1'b0;
- end
-
-end
-
-
-//MOBEAM RESET
-always @(posedge clk_i or posedge rst_i) begin
- if (rst_i) begin
- rst_mobeam<=1'b0;
-
- end
-else
- if (i2c_slave_data_address_i == 8'hF1)
- if (wr_en & (i2c_master_to_slave_data_i==8'b00000001))begin
- rst_mobeam<=1'b1;
- end
- else if(wr_en & (i2c_master_to_slave_data_i==8'b00000000))begin
- rst_mobeam<=1'b0;
- end
-
-end
-
-//REVISION CODE
-always @(posedge clk_i or posedge rst_i) begin
- if (rst_i) begin
- rd_revision_code<=1'b0;
-
- end
-else
- if (rd_en)begin
- if (i2c_slave_data_address_i == 8'hF2) begin
- rd_revision_code<=1'b1;
- i2c_slave_to_master_data_o<=revision_code;
- end
- else begin
- rd_revision_code<=1'b0;
- i2c_slave_to_master_data_o<=0;
- end
- end
- else
- i2c_slave_to_master_data_o<=0;
-
-end
-
-//LED POLARITY
-always @(posedge clk_i or posedge rst_i) begin
- if (rst_i) begin
- led_polarity<=1'b0;
-
- end else begin
- //if (wr_en)begin
- //if (i2c_slave_data_address_i == 8'hEB)begin
- //if (i2c_master_to_slave_data_i==8'b00000001)begin
- led_polarity<=1'b1;
- //end else begin
- //led_polarity<=1'b0;
- //end
- //end
- //end
- end
-end
-
-reg ba_wr_en_delayed;
-reg wr_en_cnt;
-reg [7:0] ba_mem_addr_in_delayed,ba_mem_addr_in_delayed_1;
-reg [7:0] data_buffer;
-reg [15:0] ba_mem_data_buffer;
-
-
-always @(posedge clk_i or posedge rst_i) begin
- if (rst_i) begin
- ba_mem_addr_in_delayed<=8'd0;
- ba_mem_addr_in_delayed_1<=8'd0;
- ba_wr_en_delayed<= 1'b0;
-
- end
-else begin
- ba_mem_addr_in_delayed<= ba_mem_addr_in;
- ba_mem_addr_in_delayed_1<= ba_mem_addr_in_delayed;
- ba_wr_en_delayed<= ba_wr_en;
-
-end
-end
-
-
-
-
-
-//assign ba_mem_data_buffer = { i2c_master_to_slave_data_i,data_buffer};
-always @(posedge clk_i or posedge rst_i) begin
- if (rst_i) begin
- ba_mem_addr_in <= 9'd0;
- ba_wr_en<= 1'b0;
- wr_en_cnt<= 1'b0;
- end
-else
-
- if (i2c_slave_data_address_i == 8'h00) begin
-
- if (wr_en_cnt) begin
- ba_mem_data_buffer <= { i2c_master_to_slave_data_i,data_buffer};
- end
-
-
- if (wr_en) begin
- wr_en_cnt<= wr_en_cnt + 1'b1;
- ba_wr_en<= 1'b1;
- if (~wr_en_cnt)begin
- data_buffer <= i2c_master_to_slave_data_i;
- end
- else
- ba_mem_addr_in <= ba_mem_addr_in + 1'b1;
- end
- else
- ba_wr_en<= 1'b0;
-
- end
- else begin
- ba_mem_addr_in<=0;
- ba_wr_en<= 1'b0;
- wr_en_cnt<=0;
- end
-
-end
-endmodule
\ No newline at end of file
diff --git a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/testpll_pll_20_25Mhz.v b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/testpll_pll_20_25Mhz.v
deleted file mode 100644
index f2d0b0a68..000000000
--- a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/testpll_pll_20_25Mhz.v
+++ /dev/null
@@ -1,82 +0,0 @@
-//==================================================================
-// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-// ------------------------------------------------------------------
-// Copyright (c) 2014 by Lattice Semiconductor Corporation
-// ALL RIGHTS RESERVED
-// ------------------------------------------------------------------
-//
-// Permission:
-//
-// Lattice SG Pte. Ltd. grants permission to use this code for use
-// in synthesis for any Lattice programmable logic product. Other
-// use of this code, including the selling or duplication of any
-// portion is strictly prohibited.
-
-//
-// Disclaimer:
-//
-// This VHDL or Verilog source code is intended as a design reference
-// which illustrates how these types of functions can be implemented.
-// It is the user's responsibility to verify their design for
-// consistency and functionality through the use of formal
-// verification methods. Lattice provides no warranty
-// regarding the use or functionality of this code.
-//
-// --------------------------------------------------------------------
-//
-// Lattice SG Pte. Ltd.
-// 101 Thomson Road, United Square #07-02
-// Singapore 307591
-//
-//
-// TEL: 1-800-Lattice (USA and Canada)
-// +65-6631-2000 (Singapore)
-// +1-503-268-8001 (other locations)
-//
-// web: http://www.latticesemi.com/
-// email: techsupport@latticesemi.com
-//
-// --------------------------------------------------------------------
-//
-
-
-module testpll_pll(REFERENCECLK,
- PLLOUTCORE,
- PLLOUTGLOBAL,
- RESET,
- LOCK);
-
-input REFERENCECLK;
-input RESET; /* To initialize the simulation properly, the RESET signal (Active Low) must be asserted at the beginning of the simulation */
-output PLLOUTCORE;
-output PLLOUTGLOBAL;
-output LOCK;
-
-SB_PLL40_CORE testpll_pll_inst(.REFERENCECLK(REFERENCECLK),
- .PLLOUTCORE(PLLOUTCORE),
- .PLLOUTGLOBAL(PLLOUTGLOBAL),
- .EXTFEEDBACK(),
- .DYNAMICDELAY(),
- .RESETB(RESET),
- .BYPASS(1'b0),
- .LATCHINPUTVALUE(),
- .LOCK(LOCK),
- .SDI(),
- .SDO(),
- .SCLK());
-
-//\\ Fin=27, Fout=20.05;
-defparam testpll_pll_inst.DIVR = 4'b0000;
-defparam testpll_pll_inst.DIVF = 7'b0010111;
-defparam testpll_pll_inst.DIVQ = 3'b101;
-defparam testpll_pll_inst.FILTER_RANGE = 3'b011;
-defparam testpll_pll_inst.FEEDBACK_PATH = "SIMPLE";
-defparam testpll_pll_inst.DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
-defparam testpll_pll_inst.FDA_FEEDBACK = 4'b0000;
-defparam testpll_pll_inst.DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
-defparam testpll_pll_inst.FDA_RELATIVE = 4'b0000;
-defparam testpll_pll_inst.SHIFTREG_DIV_MODE = 2'b00;
-defparam testpll_pll_inst.PLLOUT_SELECT = "GENCLK";
-defparam testpll_pll_inst.ENABLE_ICEGATE = 1'b0;
-
-endmodule
diff --git a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/top_module.v b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/top_module.v
deleted file mode 100644
index 77af4ca73..000000000
--- a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/top_module.v
+++ /dev/null
@@ -1,334 +0,0 @@
-//==================================================================
-// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-// ------------------------------------------------------------------
-// Copyright (c) 2014 by Lattice Semiconductor Corporation
-// ALL RIGHTS RESERVED
-// ------------------------------------------------------------------
-//
-// Permission:
-//
-// Lattice SG Pte. Ltd. grants permission to use this code for use
-// in synthesis for any Lattice programmable logic product. Other
-// use of this code, including the selling or duplication of any
-// portion is strictly prohibited.
-
-//
-// Disclaimer:
-//
-// This VHDL or Verilog source code is intended as a design reference
-// which illustrates how these types of functions can be implemented.
-// It is the user's responsibility to verify their design for
-// consistency and functionality through the use of formal
-// verification methods. Lattice provides no warranty
-// regarding the use or functionality of this code.
-//
-// --------------------------------------------------------------------
-//
-// Lattice SG Pte. Ltd.
-// 101 Thomson Road, United Square #07-02
-// Singapore 307591
-//
-//
-// TEL: 1-800-Lattice (USA and Canada)
-// +65-6631-2000 (Singapore)
-// +1-503-268-8001 (other locations)
-//
-// web: http://www.latticesemi.com/
-// email: techsupport@latticesemi.com
-//
-// --------------------------------------------------------------------
-//
-
-//`define SIM
-`define i2c
-//`define spi
-//`define uart
-
-
-
-module top_module
- // Outputs
- ( o_led,
- // Inouts
- `ifdef i2c
- io_i2c_scl, io_i2c_sda,
- `endif
- //spi signals
- `ifdef spi
- i_sck, i_csn, i_mosi,o_miso,
- `endif
- `ifdef uart
- o_tx,i_rx,
- `endif
- //testpoints
- drive_on,
- // Inputs
- i_clk
- )/*synthesis syn_dspstyle=logic*/;
-
- //input i_rst;
-
- output wire o_led;
- output drive_on;
- input i_clk;
-`ifdef i2c
- inout io_i2c_scl;
- inout io_i2c_sda;
-`endif
-`ifdef spi
- input i_sck;
- input i_csn;
- input i_mosi;
- output o_miso;
-`endif
-`ifdef uart
- output o_tx;
- input i_rx;
-`endif
- wire sclin_i;
- wire sdain_i;
- wire sdaout_i;
- wire [7:0] datain_i;
- wire write_en_i;
- wire [7:0] dataout_i;
- wire [7:0] regaddr_i;
- wire read_en_i;
- reg [15:0] poweron_reset_count_i = 0; //initialized for simulation
- reg poweron_reset_n_i = 0; // initialized for simulation
- wire rst_i;
-
-//mobeam control logic interface//
-wire [15:0] o_ba_mem_data;
-wire [7:0] i_ba_mem_addr;
-wire i_ba_mem_rd_en;
-wire i_ba_mem_rd_clk;
-wire rd_revision_code;
-wire rst_mobeam;
-wire [7:0] o_bsr_mem_data;
-wire [8:0] i_bsr_mem_addr;
-wire i_bsr_mem_rd_en;
-wire i_bsr_mem_rd_clk;
-wire o_new_data_rd;
-wire o_bsr_data_strobe;
-wire i_config_reg_done;
-////////////////////////////////
-wire clk_20mhz_g;
-
-testpll_pll testpll_pll_inst(.REFERENCECLK(i_clk),
- .PLLOUTCORE(),
- .PLLOUTGLOBAL(clk_20mhz_g),
- .RESET(~rst_i/*1'b1*/),
- .LOCK());
-
-//selection of SPI or I2C///
-`ifdef spi
-user_logic_control_reg_spidata_buf spi_mobeam_logic_interface
-(
-///spi Signal/////
- .i_sys_clk(i_clk),
- .rst(rst_i),
- .i_sck(i_sck),
- .i_csn(i_csn),
- .i_mosi(i_mosi),
- .o_miso(o_miso),
-///Mobeam Control Signals///
- .rd_revision_code(rd_revision_code),
- .rst_mobeam(rst_mobeam),
- .led_polarity(led_polarity),
- .mobeam_start_stop(mobeam_start_stop),
- .o_ba_mem_data(o_ba_mem_data),
- .i_ba_mem_addr(i_ba_mem_addr),
- .i_ba_mem_rd_en(i_ba_mem_rd_en),
- .i_ba_mem_rd_clk(i_ba_mem_rd_clk),
- .o_bsr_mem_data(o_bsr_mem_data),
- .i_bsr_mem_addr(i_bsr_mem_addr),
- .i_bsr_mem_rd_en(i_bsr_mem_rd_en),
- .i_bsr_mem_rd_clk(i_bsr_mem_rd_clk)
-// .i_config_reg_done(i_config_reg_done),
-// .o_new_data_rd(o_new_data_rd),
-// .o_data_strobe(o_bsr_data_strobe)
-);
-`endif
-
-`ifdef i2c
-user_logic_control_reg_data_buf i2c_mobeam_logic_interface
-(
-///i2c Signal/////
- .clk(clk_20mhz_g),
- .rst(rst_i),
- .scl(sclin_i),
- .sdaout(sdaout_i),
- .sdaIn(sdain_i),
-///Mobeam Control Signals///
- .rd_revision_code(rd_revision_code),
- .rst_mobeam(rst_mobeam),
- .led_polarity(led_polarity),
- .mobeam_start_stop(mobeam_start_stop),
- .o_ba_mem_data(o_ba_mem_data),
- .i_ba_mem_addr(i_ba_mem_addr),
- .i_ba_mem_rd_en(i_ba_mem_rd_en),
- .i_ba_mem_rd_clk(i_ba_mem_rd_clk),
- .o_bsr_mem_data(o_bsr_mem_data),
- .i_bsr_mem_addr(i_bsr_mem_addr),
- .i_bsr_mem_rd_en(i_bsr_mem_rd_en),
- .i_bsr_mem_rd_clk(i_bsr_mem_rd_clk)
-// .i_config_reg_done(i_config_reg_done),
-// .o_new_data_rd(o_new_data_rd),
-// .o_data_strobe(o_bsr_data_strobe)
-);
-`endif
-
-//--------------------------------------------------------------
- //uart module instantiation
-`ifdef uart
- uart_top u_inst(
- .i_sys_clk (clk_20mhz_g),
- .i_sys_rst (rst_i),
- .i_rx (i_rx),
- //outputs
- .o_tx (o_tx),
- .o_done (done_i),
- ///Mobeam Control Signals
- .rd_revision_code (rd_revision_code),
- .rst_mobeam (rst_mobeam),
- .led_polarity (led_polarity),
- .mobeam_start_stop (mobeam_start_stop),
- .o_ba_mem_data (o_ba_mem_data),
- .i_ba_mem_addr (i_ba_mem_addr),
- .i_ba_mem_rd_en (i_ba_mem_rd_en),
- .i_ba_mem_rd_clk (i_ba_mem_rd_clk),
- .o_bsr_mem_data (o_bsr_mem_data),
- .i_bsr_mem_addr (i_bsr_mem_addr),
- .i_bsr_mem_rd_en (i_bsr_mem_rd_en),
- .i_bsr_mem_rd_clk (i_bsr_mem_rd_clk)
- );
-`endif
-///////////////////////////////////////////////////////
-
-////MobeamControlFSM//////
-mobeam_control_fsm fsm_mobeam(
- .sys_clk_i(clk_20mhz_g),
- ///Mobeam Control Signals///
- .start_stop(mobeam_start_stop),
- .rst_mobeam(rst_mobeam|rst_i),
- //bsr memory signals
- .bsr_mem_data(o_bsr_mem_data),
- .bsr_mem_clk(i_bsr_mem_rd_clk),
- .bsr_mem_addr(i_bsr_mem_addr),
- .bsr_mem_rd_en(i_bsr_mem_rd_en),
-
- //ba memory signals
- .ba_mem_data(o_ba_mem_data),
- .ba_mem_clk(i_ba_mem_rd_clk),
- .ba_mem_addr(i_ba_mem_addr),
- .ba_mem_rd_en(i_ba_mem_rd_en),
-
- //TO LED DRIVER
- .o_byte_data(barcode_array),
- .shift_done(byte_done),
- .bit_done(bit_done),
- .txn_start(txn_start),
- // .bsr_load_done(),
- .bsr_bw(bar_width)
-
-);
-
-wire [7:0] bar_width, barcode_array;
-/////LED Driver//////
-led_driver led_drive_inst (
- .sys_clk(clk_20mhz_g),
- .mobeam_start_stop(mobeam_start_stop),
- .led_polarity(led_polarity),
- .rst_n(~rst_i|rst_mobeam),
- .txn_start(txn_start),
- .bar_width(bar_width),
- .barcode_array(barcode_array),
- .byte_done(byte_done),
- .bit_done(bit_done),
- .drive_on(drive_on),
- .oled(o_led)
- //output dynamic_clk);
- );
-////////////////////////////////////////
-
-////////////////////////////////////////////////
-/////oled data verification/////////////////////
- `ifdef SIM
-
-reg [7:0] capture_oled=0;
-reg [7:0] oled_check=0;
-integer i=8;
-integer mon;
-
-
-initial begin
- mon = $fopen("monitor.txt","w"); //file to write
-end
-
-always @(posedge i_clk) begin
-// $fwrite(mon,"%h \n",oled_check);
- if(txn_start && /*rise_reload_ba_reg_dtc*/fall_reload_ba_reg_dtc) begin
- //if(led_polarity)
- capture_oled[i]= o_led;
- //else
- // capture_oled[i]= ~o_led;
- end
- end
-
- always @( negedge fall_reload_ba_reg_dtc) begin
- if(i==0) begin
- oled_check=capture_oled;
-
- i<=7;
- end
- else
-
- i<=i-1;
- end
-
-
-always @(posedge i_clk) begin
- if(txn_start && byte_done)
- $fwrite(mon,"%h \n",oled_check);
- end
-
-
- reg q_reload_ba_reg;
-always @(posedge i_clk or posedge rst_i) begin
- if(rst_i)
- q_reload_ba_reg<=0;
- else
- q_reload_ba_reg<=led_drive_inst.reload_ba_reg;
- end
-assign rise_reload_ba_reg_dtc=(~q_reload_ba_reg) && led_drive_inst.reload_ba_reg;
-
-assign fall_reload_ba_reg_dtc=(q_reload_ba_reg) && (~led_drive_inst.reload_ba_reg);
-
-`endif
-
-//end
-///////////////////////////////////////////////////////////////
-///////////////////////////////////////////////////////////////
-`ifdef i2c
- assign io_i2c_sda = (sdaout_i == 1'b0) ? 1'b0 : 1'bz;
- assign sdain_i = io_i2c_sda;
- assign sclin_i = io_i2c_scl;
-`endif
-
- always @(posedge i_clk)begin
- if(poweron_reset_count_i == 256)begin
- poweron_reset_count_i <= 256;
- end else begin
- poweron_reset_count_i <= poweron_reset_count_i + 1;
- end
- end
-
- always @(posedge i_clk)begin
- if(poweron_reset_count_i == 256)begin
- poweron_reset_n_i <= 1;
- end else begin
- poweron_reset_n_i <= 0;
- end
- end
- assign rst_i = ~poweron_reset_n_i;
-endmodule // i2c_slave
\ No newline at end of file
diff --git a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/user_logic_control_reg_i2c_data_buf.v b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/user_logic_control_reg_i2c_data_buf.v
deleted file mode 100644
index e3b434533..000000000
--- a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/user_logic_control_reg_i2c_data_buf.v
+++ /dev/null
@@ -1,138 +0,0 @@
-//==================================================================
-// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-// ------------------------------------------------------------------
-// Copyright (c) 2014 by Lattice Semiconductor Corporation
-// ALL RIGHTS RESERVED
-// ------------------------------------------------------------------
-//
-// Permission:
-//
-// Lattice SG Pte. Ltd. grants permission to use this code for use
-// in synthesis for any Lattice programmable logic product. Other
-// use of this code, including the selling or duplication of any
-// portion is strictly prohibited.
-
-//
-// Disclaimer:
-//
-// This VHDL or Verilog source code is intended as a design reference
-// which illustrates how these types of functions can be implemented.
-// It is the user's responsibility to verify their design for
-// consistency and functionality through the use of formal
-// verification methods. Lattice provides no warranty
-// regarding the use or functionality of this code.
-//
-// --------------------------------------------------------------------
-//
-// Lattice SG Pte. Ltd.
-// 101 Thomson Road, United Square #07-02
-// Singapore 307591
-//
-//
-// TEL: 1-800-Lattice (USA and Canada)
-// +65-6631-2000 (Singapore)
-// +1-503-268-8001 (other locations)
-//
-// web: http://www.latticesemi.com/
-// email: techsupport@latticesemi.com
-//
-// --------------------------------------------------------------------
-//
-
-
-module user_logic_control_reg_data_buf
-(
-///i2c signal/////
- clk,
- rst,
- scl,
- sdaout,
- sdaIn,
-///mobeam control signals///
- rd_revision_code,
- rst_mobeam,
- led_polarity,
- mobeam_start_stop,
- o_ba_mem_data,
- i_ba_mem_addr,
- i_ba_mem_rd_en,
- i_ba_mem_rd_clk,
- o_bsr_mem_data,
- i_bsr_mem_addr,
- i_bsr_mem_rd_en,
- i_bsr_mem_rd_clk
-);
-///////i2c signals interface///////
-input clk;
-input rst;
-inout scl;
-output sdaout;
-input sdaIn;
-//////////////////////////////////
-//mobeam control logic interface//
-output [15:0] o_ba_mem_data;
-input [7:0] i_ba_mem_addr;
-input i_ba_mem_rd_en;
-input i_ba_mem_rd_clk;
-output rd_revision_code;
-output rst_mobeam;
-output mobeam_start_stop;
-output [7:0] o_bsr_mem_data;
-input [8:0] i_bsr_mem_addr;
-input i_bsr_mem_rd_en;
-input i_bsr_mem_rd_clk;
-
-output led_polarity;
-
-//////////////////////////////////
-///////wires and reg declarations////
-wire[7:0]dataOut;
-wire[7:0]regAddr;
-wire writeEn;
-wire readEn;
-wire i2c_start;
-wire[7:0]dataIn;
-///////////////////////////////////////
-serialInterface i2cslavedatafsm(/*AUTOARG*/
- // Outputs
- .dataOut(dataOut),
- .regAddr(regAddr),
- .sdaOut(sdaout),
- .writeEn(writeEn),
- .readEn(readEn),
- .i2c_start(i2c_start),
- // Inputs
- .clk(clk),
- .dataIn(dataIn),
- .rst(rst),
- .scl(scl),
- .sdaIn(sdaIn)
- );
-
-
- /*mobeam_reg_sets*/mobeam_i2c_reg_interface mobeam_registers(
- .rst_i(rst),
- .clk_i(clk),
- //i2c slave interface signals///
- .i2c_master_to_slave_data_i(dataOut),
- .i2c_slave_to_master_data_o(dataIn),
- .i2c_slave_data_address_i(regAddr),
- .wr_en_i(writeEn),
- .rd_en_i(readEn),
- .i2c_start_i(i2c_start),
- //MoBeam control logic interface//
- .rd_revision_code(rd_revision_code),
- .rst_mobeam(rst_mobeam),
- .led_polarity(led_polarity),
- .mobeam_start_stop(mobeam_start_stop),
- .o_ba_mem_data(o_ba_mem_data),
- .i_ba_mem_addr(i_ba_mem_addr),
- .i_ba_mem_rd_en(i_ba_mem_rd_en),
- .i_ba_mem_rd_clk(i_ba_mem_rd_clk),
- .o_bsr_mem_data(o_bsr_mem_data),
- .i_bsr_mem_addr(i_bsr_mem_addr),
- .i_bsr_mem_rd_en(i_bsr_mem_rd_en),
- .i_bsr_mem_rd_clk(i_bsr_mem_rd_clk)
- );
-
-endmodule
\ No newline at end of file
diff --git a/fpga_flow/configs/lattice_benchmark.conf b/fpga_flow/configs/lattice_benchmark.conf
deleted file mode 100644
index 7d270f6e3..000000000
--- a/fpga_flow/configs/lattice_benchmark.conf
+++ /dev/null
@@ -1,31 +0,0 @@
-# Standard Configuration Example
-[dir_path]
-script_base = OPENFPGAPATHKEYWORD/fpga_flow/scripts/
-benchmark_dir = OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller
-yosys_path = OPENFPGAPATHKEYWORD/yosys/yosys
-odin2_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/odin2.exe
-cirkit_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/cirkit
-abc_path = OPENFPGAPATHKEYWORD/yosys/yosys-abc
-abc_mccl_path = OPENFPGAPATHKEYWORD/abc_with_bb_support/abc
-abc_with_bb_support_path = OPENFPGAPATHKEYWORD/abc_with_bb_support/abc
-mpack1_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/mpack1
-m2net_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/m2net
-mpack2_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/mpack2
-vpr_path = OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/vpr
-rpt_dir = OPENFPGAPATHKEYWORD/fpga_flow/results
-ace_path = OPENFPGAPATHKEYWORD/ace2/ace
-
-[flow_conf]
-#Flow Types standard|mpack2|mpack1|vtr_standard|vtr|yosys_vpr
-flow_type = yosys_vpr
-vpr_arch = OPENFPGAPATHKEYWORD/fpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml
-mpack1_abc_stdlib = Not_Required
-m2net_conf = Not_Required
-mpack2_arch = Not_Required
-power_tech_xml = OPENFPGAPATHKEYWORD/fpga_flow/tech/winbond90nm/winbond90nm_power_properties.xml
-
-[csv_tags]
-mpack1_tags = Global mapping efficiency: | efficiency: | occupancy wo buf: | efficiency wo buf:
-mpack2_tags = BLE Number: | BLE Fill Rate:
-vpr_tags = Netlist clb blocks: | Final critical path: | Total logic delay: | total net delay: | Total routing area: | Total used logic block area: | Total wirelength: | Packing took | Placement took | Routing took | Average net density: | Median net density: | Recommend no. of clock cycles:
-vpr_power_tags = PB Types | Routing | Switch Box | Connection Box | Primitives | Interc Structures | lut6 | ff
diff --git a/vpr7_x2p/vpr/ARCH/k6_ReRAM_Winbond.xml b/vpr7_x2p/vpr/ARCH/k6_ReRAM_Winbond.xml
deleted file mode 100755
index f7cc298a6..000000000
--- a/vpr7_x2p/vpr/ARCH/k6_ReRAM_Winbond.xml
+++ /dev/null
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