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add routing chan width corrector to rr_graph builder utils

This commit is contained in:
tangxifan 2020-03-06 14:54:40 -07:00
parent 441de12936
commit 441a307100
3 changed files with 19 additions and 5 deletions
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15
vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp
View File

@ -15,6 +15,21 @@
/* begin namespace openfpga */
namespace openfpga {
/************************************************************************
* Correct number of routing channel width to be compatible to
* uni-directional routing architecture
***********************************************************************/
size_t find_unidir_routing_channel_width(const size_t& chan_width) {
size_t actual_chan_width = chan_width;
/* Correct the chan_width: it should be an even number */
if (0 != actual_chan_width % 2) {
actual_chan_width++; /* increment it to be even */
}
VTR_ASSERT(0 == actual_chan_width % 2);
return actual_chan_width;
}
/************************************************************************
* Get the class index of a grid pin
***********************************************************************/

2
vpr/src/tileable_rr_graph/rr_graph_builder_utils.h
View File

@ -15,6 +15,8 @@
/* begin namespace openfpga */
namespace openfpga {
size_t find_unidir_routing_channel_width(const size_t& chan_width);
int get_grid_pin_class_index(const t_grid_tile& cur_grid,
const int pin_index);

7
vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp
View File

@ -11,6 +11,7 @@
#include "vtr_assert.h"
#include "vtr_log.h"
#include "rr_graph_builder_utils.h"
#include "tileable_chan_details_builder.h"
/* begin namespace openfpga */
@ -167,11 +168,7 @@ ChanNodeDetails build_unidir_chan_node_details(const size_t& chan_width,
const bool& force_end,
const std::vector<t_segment_inf>& segment_inf) {
ChanNodeDetails chan_node_details;
size_t actual_chan_width = chan_width;
/* Correct the chan_width: it should be an even number */
if (0 != actual_chan_width % 2) {
actual_chan_width++; /* increment it to be even */
}
size_t actual_chan_width = find_unidir_routing_channel_width(chan_width);
VTR_ASSERT(0 == actual_chan_width % 2);
/* Reserve channel width */