[Benchmark] Add a micro benchmark to test pipelined architecture

openfpga_flow/benchmarks/micro_benchmark/and2_pipelined/and2_pipelined.act

@@ -0,0 +1,7 @@
+a 0.5 0.2
+b 0.5 0.2
+c 0.25 0.1
+a_reg 0.5 0.2
+b_reg 0.5 0.2
+c_reg 0.25 0.1
+clk 0.500000 2.000000

openfpga_flow/benchmarks/micro_benchmark/and2_pipelined/and2_pipelined.blif

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+.model and2_pipelined
+.inputs clk a b
+.outputs c
+
+.latch a a_reg re clk 0
+.latch b b_reg re clk 0
+.latch c_reg c re clk 0
+
+.names a_reg b_reg c_reg
+11 1
+
+.end

openfpga_flow/benchmarks/micro_benchmark/and2_pipelined/and2_pipelined.v

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+/////////////////////////////////////////
+//  Functionality: a pipelined 2-input AND 
+//                 where inputs and outputs are registered
+//  Author:        Xifan Tang
+////////////////////////////////////////
+`timescale 1ns / 1ps
+
+module and2_pipelined(
+  clk,
+  a,
+  b,
+  c);
+
+input wire clk;
+input wire a;
+input wire b;
+output wire c;
+
+reg a_reg;
+reg b_reg;
+reg c_reg;
+
+always @(posedge clk) begin
+  a_reg <= a;
+  b_reg <= a;
+end
+
+always @(posedge clk) begin
+  c_reg <= a_reg & b_reg;
+end
+
+assign c = c_reg;
+
+endmodule