diff --git a/fpga_flow/scripts/fpga_flow.pl b/fpga_flow/scripts/fpga_flow.pl
index 92111bb87..606692373 100644
--- a/fpga_flow/scripts/fpga_flow.pl
+++ b/fpga_flow/scripts/fpga_flow.pl
@@ -159,6 +159,7 @@ sub print_usage()
   print "      \t-vpr_fpga_x2p_rename_illegal_port : turn on renaming illegal ports option of VPR FPGA SPICE\n";
   print "      \t-vpr_fpga_x2p_signal_density_weight <float>: specify the option signal_density_weight of VPR FPGA SPICE\n";
   print "      \t-vpr_fpga_x2p_sim_window_size <float>: specify the option sim_window_size of VPR FPGA SPICE\n";
+  print "      \t-vpr_fpga_x2p_compact_routing_hierarchy : allow routing block modularization\n";
   print "      [ VPR - FPGA-SPICE Extension ] \n";
   print "      \t-vpr_fpga_spice <task_file> : turn on SPICE netlists print-out in VPR, specify a task file\n";
   print "      \t-vpr_fpga_spice_sim_mt_num <int>: specify the option sim_mt_num of VPR FPGA SPICE\n";
@@ -168,6 +169,7 @@ sub print_usage()
   print "      \t-vpr_fpga_spice_leakage_only : turn on leakage_only mode in VPR FPGA SPICE\n";
   print "      \t-vpr_fpga_spice_parasitic_net_estimation_off : turn off parasitic_net_estimation in VPR FPGA SPICE\n";
   print "      \t-vpr_fpga_spice_testbench_load_extraction_off : turn off testbench_load_extraction in VPR FPGA SPICE\n";
+  print "      \t-vpr_fpga_spice_simulator_path <string> : Specify simulator path\n";
   print "      [ VPR - FPGA-Verilog Extension ] \n";
   print "      \t-vpr_fpga_verilog : turn on Verilog Generator of VPR FPGA SPICE\n";
   print "      \t-vpr_fpga_verilog_dir <verilog_path>: provide the path where generated verilog files will be written\n";
@@ -338,6 +340,7 @@ sub opts_read()
   &read_opt_into_hash("vpr_fpga_x2p_rename_illegal_port","off","off");
   &read_opt_into_hash("vpr_fpga_x2p_signal_density_weight","on","off");
   &read_opt_into_hash("vpr_fpga_x2p_sim_window_size","on","off");
+  &read_opt_into_hash("vpr_fpga_x2p_compact_routing_hierarchy","off","off");
   &read_opt_into_hash("vpr_fpga_spice_sim_mt_num","on","off");
   &read_opt_into_hash("vpr_fpga_spice_print_component_tb","off","off");
   &read_opt_into_hash("vpr_fpga_spice_print_grid_tb","off","off");
@@ -345,6 +348,7 @@ sub opts_read()
   &read_opt_into_hash("vpr_fpga_spice_leakage_only","off","off");
   &read_opt_into_hash("vpr_fpga_spice_parasitic_net_estimation_off","off","off");
   &read_opt_into_hash("vpr_fpga_spice_testbench_load_extraction_off","off","off");
+  &read_opt_into_hash("vpr_fpga_spice_simulator_path","on","off");
 
   # FPGA-Verilog options
   # Read Opt into Hash(opt_ptr) : "opt_name","with_val","mandatory"
@@ -1323,9 +1327,15 @@ sub run_std_vpr($ $ $ $ $ $ $ $ $)
     if ("on" eq $opt_ptr->{vpr_fpga_x2p_sim_window_size}) {
       $vpr_spice_opts = $vpr_spice_opts." --fpga_x2p_sim_window_size $opt_ptr->{vpr_fpga_x2p_sim_window_size_val}";
     }
+    if ("on" eq $opt_ptr->{vpr_fpga_x2p_compact_routing_hierarchy}) {
+      $vpr_spice_opts = $vpr_spice_opts." --fpga_x2p_compact_routing_hierarchy";
+    }
     if ("on" eq $opt_ptr->{vpr_fpga_spice_sim_mt_num}) {
       $vpr_spice_opts = $vpr_spice_opts." --fpga_spice_sim_mt_num $opt_ptr->{vpr_fpga_spice_sim_mt_num_val}";
     }
+    if ("on" eq $opt_ptr->{vpr_fpga_spice_simulator_path}) {
+      $vpr_spice_opts = $vpr_spice_opts." --fpga_spice_simulator_path $opt_ptr->{vpr_fpga_spice_simulator_path_val}";
+    }
     if ("on" eq $opt_ptr->{vpr_fpga_spice_print_component_tb}) {
       $vpr_spice_opts = $vpr_spice_opts." --fpga_spice_print_lut_testbench";
       $vpr_spice_opts = $vpr_spice_opts." --fpga_spice_print_hardlogic_testbench";