riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[test] make arch pin loc for spread for perimeter cb validation

This commit is contained in:
tangxifan 2024-07-06 12:11:31 -07:00
parent 6024e35f89
commit 43ca3ec747
1 changed files with 8 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml
View File

@ -93,9 +93,9 @@
<output name="inpad" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="custom">
<loc side="left">fpga_input[0:3].inpad</loc>
<loc side="left">fpga_input[0:1].inpad</loc>
<loc side="right"></loc>
<loc side="top"></loc>
<loc side="top">fpga_input[2:3].inpad</loc>
<loc side="bottom"></loc>
</pinlocations>
</sub_tile>
@ -106,9 +106,9 @@
<input name="outpad" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="custom">
<loc side="left">fpga_output[0:1].outpad</loc>
<loc side="left">fpga_output[0:0].outpad</loc>
<loc side="right"></loc>
<loc side="top"></loc>
<loc side="top">fpga_output[1:1].outpad</loc>
<loc side="bottom"></loc>
</pinlocations>
</sub_tile>
@ -122,8 +122,8 @@
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="custom">
<loc side="left"></loc>
<loc side="right"></loc>
<loc side="top">fpga_input.inpad</loc>
<loc side="right">fpga_input[0:1].inpad</loc>
<loc side="top">fpga_input[2:3].inpad</loc>
<loc side="bottom"></loc>
</pinlocations>
</sub_tile>
@ -135,8 +135,8 @@
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="custom">
<loc side="left"></loc>
<loc side="right"></loc>
<loc side="top">fpga_output.outpad</loc>
<loc side="right">fpga_output[0:0].outpad</loc>
<loc side="top">fpga_output[1:1].outpad</loc>
<loc side="bottom"></loc>
</pinlocations>
</sub_tile>