From 43418cd76b66ca28c66e457d6f286e404d158fe0 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 10 Jan 2021 10:28:22 -0700 Subject: [PATCH] [Test] Deploy pipeplined and2 to test cases --- .../global_tile_ports/global_tile_clock/config/task.conf | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock/config/task.conf b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock/config/task.conf index fd95b7ca9..abc1be003 100644 --- a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock/config/task.conf @@ -26,6 +26,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTileClk_ [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_pipelined/and2_pipelined.v [SYNTHESIS_PARAM] bench0_top = and2 @@ -34,5 +35,8 @@ bench0_chan_width = 300 bench1_top = and2_latch bench1_chan_width = 300 +bench2_top = and2_pipelined +bench2_chan_width = 300 + [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test=