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Clean codes and update

This commit is contained in:
Xifan Tang 2018-09-04 17:49:20 -06:00
parent 9f3cb45b85
commit 42da9160f0
2 changed files with 23 additions and 24 deletions
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23
fpga_flow/run_fpga_spice_testbench_study.sh Normal file
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@ -0,0 +1,23 @@
# Make sure a clear start
# Sweep Corner Cases
set corner_list = (TT)
#set corner_list = (TT FF SS MC)
foreach j ($corner_list)
#rm -rf ./results
cd ./scripts
if ($j == MC) then
set mc_opt = (-monte_carlo detail_rpt)
else
set mc_opt = ()
endif
perl fpga_flow.pl -conf ../configs/fpga_spice/k6_N10_sram_tsmc40nm_$j\.conf -benchmark ../benchmarks/fpga_spice_bench.txt -rpt ../csv_rpts/fpga_spice/k6_N10_sram_tsmc40nm_bench_$j\.csv -N 10 -K 6 -power -remove_designs -multi_thread 1 -vpr_fpga_spice ../vpr_fpga_spice_task_lists/k6_N10_sram_tsmc40nm -vpr_fpga_spice_rename_illegal_port -vpr_fpga_spice_sim_mt_num 16 -vpr_fpga_spice_print_top_tb -vpr_fpga_spice_print_component_tb -vpr_fpga_spice_print_grid_tb #-vpr_fpga_spice_parasitic_net_estimation_off #-vpr_fpga_spice_leakage_only
perl run_fpga_spice.pl -conf ../vpr_fpga_spice_conf/sample.conf -task ../vpr_fpga_spice_task_lists/k6_N10_sram_tsmc40nm_standard.txt -rpt ../vpr_fpga_spice_csv_rpts/k6_N10_sram_tsmc40_spice_bench_$j\.csv $mc_opt -parse_top_tb -multi_thread 6 -parse_pb_mux_tb -parse_cb_mux_tb -parse_sb_mux_tb -parse_lut_tb -parse_hardlogic_tb -parse_grid_tb -parse_cb_tb -parse_sb_tb
cd ..
end

24
fpga_flow/scripts/fpga_flow.pl
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@ -165,11 +165,6 @@ sub print_usage()
print " \t-vpr_fpga_spice_testbench_load_extraction_off : turn off testbench_load_extraction in VPR FPGA SPICE\n";
print " [ VPR - FPGA-Verilog Extension ] \n";
print " \t-vpr_fpga_verilog : turn on Verilog Generator of VPR FPGA SPICE\n";
print " \t-vpr_fpga_verilog_print_top_tb : turn on printing top-level testbench for Verilog Generator of VPR FPGA SPICE\n";
print " \t-vpr_fpga_verilog_print_input_blif_tb : turn on printing testbench for input blif file in Verilog Generator of VPR FPGA SPICE\n";
print " \t-vpr_fpga_verilog_print_compact_netlist: turn on printing compact Verilog netlists in Verilog Generator of VPR FPGA SPICE\n";
print " [ VPR - FPGA-Bitstream Extension ] \n";
print " \t-vpr_fpga_bitstream_generator: turn on FPGA-SPICE bitstream generator\n";
exit(1);
return 1;
}
@ -335,10 +330,6 @@ sub opts_read()
&read_opt_into_hash("vpr_fpga_spice_parasitic_net_estimation_off","off","off");
&read_opt_into_hash("vpr_fpga_spice_testbench_load_extraction_off","off","off");
&read_opt_into_hash("vpr_fpga_verilog","off","off");
&read_opt_into_hash("vpr_fpga_verilog_print_top_tb","off","off");
&read_opt_into_hash("vpr_fpga_verilog_print_input_blif_tb","off","off");
&read_opt_into_hash("vpr_fpga_verilog_print_compact_netlist","off","off");
&read_opt_into_hash("vpr_fpga_bitstream_generator","off","off");
&print_opts();
@ -1143,21 +1134,6 @@ sub run_std_vpr($ $ $ $ $ $ $ $ $)
# FPGA Verilog options
if (("on" eq $opt_ptr->{power})&&("on" eq $opt_ptr->{vpr_fpga_verilog})) {
$vpr_spice_opts = $vpr_spice_opts." --fpga_verilog";
if ("on" eq $opt_ptr->{vpr_fpga_verilog_print_top_tb}) {
$vpr_spice_opts = $vpr_spice_opts." --fpga_verilog_print_top_testbench";
}
if ("on" eq $opt_ptr->{vpr_fpga_verilog_print_input_blif_tb}) {
$vpr_spice_opts = $vpr_spice_opts." --fpga_verilog_print_input_blif_testbench";
}
if ("on" eq $opt_ptr->{vpr_fpga_verilog_print_compact_netlist}) {
$vpr_spice_opts = $vpr_spice_opts." --fpga_verilog_compact_netlist";
}
}
# FPGA Bitstream Generator Options
if ("on" eq $opt_ptr->{vpr_fpga_bitstream_generator}) {
$vpr_spice_opts = $vpr_spice_opts." --fpga_bitstream_generator";
}
if (("on" eq $opt_ptr->{vpr_fpga_spice_rename_illegal_port})