diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_adder_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_adder_flow.ys
deleted file mode 100644
index 56c27123a..000000000
--- a/openfpga_flow/misc/ys_tmpl_yosys_vpr_adder_flow.ys
+++ /dev/null
@@ -1,78 +0,0 @@
-${READ_VERILOG_FILE}
-# read_verilog -lib cells_sim.v
-hierarchy -check -top ${TOP_MODULE}
-proc
-
-# flatten
-# tribuf -logic
-# deminout
-
-opt_expr
-opt_clean
-check
-opt
-wreduce
-peepopt
-opt_clean
-share
-# techmap -map +/cmp2lut.v -D LUT_WIDTH=4
-opt_expr
-opt_clean
-# ice40_dsp (if -dsp)
-alumacc
-opt
-fsm
-opt -fast
-memory -nomap
-opt_clean
-
-### BRAM
-# memory_bram -rules +/ice40/brams.txt
-# techmap -map +/ice40/brams_map.v
-# ice40_braminit
-
-### Map
-# opt -fast -mux_undef -undriven -fine
-# memory_map
-# opt -undriven -fine
-
-### map_gates
-# techmap -map +/techmap.v -map +/ice40/arith_map.v
-techmap -map ${YOSYS_ADDER_MAP_VERILOG}
-opt
-# abc -dff (only if -retime)
-# ice40_opt
-
-### map_ffs
-# dffsr2dff
-# dff2dffe -direct-match $_DFF_*
-# techmap -D NO_LUT -map +/ice40/cells_map.v
-# opt_expr -mux_undef
-# simplemap
-# ice40_ffinit
-# ice40_ffssr
-# ice40_opt -full
-stat
-### map_luts
-abc -lut ${LUT_SIZE}
-# abc (only if -abc2)
-# ice40_opt (only if -abc2)
-# techmap -map +/ice40/latches_map.v
-# simplemap (only if -noabc)
-# techmap -map +/gate2lut.v -D LUT_WIDTH=4 (only if -noabc)
-# abc -dress -lut 4 (skip if -noabc)
-# clean
-# ice40_unlut (only if -relut)
-# opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3 (only if -relut)
-
-### map_cells
-# techmap -map +/ice40/cells_map.v (with -D NO_LUT in vpr mode)
-# clean
-
-### check
-# hierarchy -check
-# stat
-# check -noinit
-### blif
-opt_clean -purge
-write_blif -conn -param ${OUTPUT_BLIF}
diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys
index 45c5fe758..9a5d5c970 100644
--- a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys
+++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys
@@ -52,9 +52,16 @@ select -clear
chtype -set $mul t:$__soft_mul# Extract arithmetic functions
#########################
-# Run coarse synthesis
+# Map $alu to carry chain
#########################
alumacc
+techmap -map ${YOSYS_ADDER_MAP_VERILOG}
+
+#########################
+# Run coarse synthesis
+#########################
+# Run a tech map with default library
+techmap
share
opt
fsm
@@ -64,10 +71,6 @@ opt -fast
memory -nomap
opt_clean
-#########################
-# Map $alu to carry chain
-#########################
-techmap -map ${YOSYS_ADDER_MAP_VERILOG}
#########################
# Map logics to BRAMs
@@ -95,8 +98,6 @@ opt_rmdff
opt_clean
opt
-stat
-
#########################
# Map LUTs
#########################
diff --git a/openfpga_flow/openfpga_arch/k4_frac_N8_adder_chain_mem1K_130nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N8_adder_chain_mem1K_130nm_cc_openfpga.xml
new file mode 100644
index 000000000..0d0d93958
--- /dev/null
+++ b/openfpga_flow/openfpga_arch/k4_frac_N8_adder_chain_mem1K_130nm_cc_openfpga.xml
@@ -0,0 +1,294 @@
+
+
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+ 10e-12
+
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+ 10e-12
+
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+
+
+
+
+ 10e-12
+
+
+ 10e-12
+
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+ 10e-12
+
+
+ 10e-12
+
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+
+
+ 10e-12 5e-12
+
+
+ 10e-12 5e-12
+
+
+
+
+
+
+
+
+
+
+
+
+ 10e-12 5e-12 5e-12
+
+
+ 10e-12 5e-12 5e-12
+
+
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diff --git a/openfpga_flow/openfpga_yosys_techlib/common/openfpga_dff_map.v b/openfpga_flow/openfpga_yosys_techlib/common/openfpga_dff_map.v
index 8c6c149c4..eae75c5d3 100644
--- a/openfpga_flow/openfpga_yosys_techlib/common/openfpga_dff_map.v
+++ b/openfpga_flow/openfpga_yosys_techlib/common/openfpga_dff_map.v
@@ -17,6 +17,16 @@ module \$_DFF_PP0_ (D, C, R, Q);
dffr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R));
endmodule
+// Async reset
+module \$_DFF_PP1_ (D, C, R, Q);
+ input D;
+ input C;
+ input R;
+ output Q;
+ parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
+ dffr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R));
+endmodule
+
// Async active-low reset
module \$_DFF_PN0_ (D, C, R, Q);
input D;
diff --git a/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_cell_sim.v b/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_cell_sim.v
index bc54335ac..61fb15469 100644
--- a/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_cell_sim.v
+++ b/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_cell_sim.v
@@ -1,4 +1,4 @@
-module carry_adder (
+module adder (
input a, b, cin,
output sumout, cout
);
diff --git a/openfpga_flow/vpr_arch/k4_frac_N8_tileable_adder_chain_mem1K_130nm.xml b/openfpga_flow/vpr_arch/k4_frac_N8_tileable_adder_chain_mem1K_130nm.xml
new file mode 100644
index 000000000..788adc002
--- /dev/null
+++ b/openfpga_flow/vpr_arch/k4_frac_N8_tileable_adder_chain_mem1K_130nm.xml
@@ -0,0 +1,930 @@
+
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+ io.outpad io.inpad
+ io.outpad io.inpad
+ io.outpad io.inpad
+ io.outpad io.inpad
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+ clb.clk
+ clb.cin
+ clb.O[7:0] clb.I[5:0] clb.reset
+ clb.cout clb.O[15:8] clb.I[11:6]
+
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