From 4242c39b01fe3e6af3dcea96ac88cf4c3892c3db Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 14 Jan 2023 23:05:04 -0800 Subject: [PATCH] [core] fixed a bug in handling design constraints in repack --- openfpga/src/repack/repack.cpp | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/openfpga/src/repack/repack.cpp b/openfpga/src/repack/repack.cpp index 6dcc64a70..db282fde8 100644 --- a/openfpga/src/repack/repack.cpp +++ b/openfpga/src/repack/repack.cpp @@ -613,6 +613,18 @@ static void add_lb_router_nets( } } else if (design_constraints.unconstrained_net(constrained_net_name)) { constrained_atom_net_id = atom_net_id; + /* Skip for the net which has been constrained on other pins */ + if (atom_net_id && !design_constraints.unconstrained_net(atom_ctx.nlist.net_name(atom_net_id))) { + VTR_LOGV(verbose, + "Skip net '%s' on pin '%s[%d]' during repacking since it has been constrained to another pin\n", + atom_ctx.nlist.net_name(atom_net_id).c_str(), source_pb_pin->port->name, + source_pb_pin->pin_number); + continue; + } + VTR_LOGV(verbose, + "Follow the same mapping results for net '%s' on pin '%s[%d]' during repacking (constrained net name is %s)\n", + atom_ctx.nlist.net_name(atom_net_id).c_str(), source_pb_pin->port->name, + source_pb_pin->pin_number, constrained_net_name.c_str()); } /* Bypass unmapped pins. There are 4 conditions to consider