From 965ee2190ecab44e0404da19cbe7600d7e526c40 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 20 Sep 2024 17:42:26 -0700 Subject: [PATCH 01/16] [core] support intermediate driver in clock arch --- .../arch/example_internal_drivers.xml | 5 ++ .../src/base/clock_network.cpp | 53 +++++++++++++++ .../src/base/clock_network.h | 7 ++ .../src/io/clock_network_xml_constants.h | 6 ++ .../src/io/read_xml_clock_network.cpp | 65 ++++++++++++++++++- .../src/io/write_xml_clock_network.cpp | 37 +++++++++++ 6 files changed, 172 insertions(+), 1 deletion(-) diff --git a/libs/libclkarchopenfpga/arch/example_internal_drivers.xml b/libs/libclkarchopenfpga/arch/example_internal_drivers.xml index d6435523c..6332695a0 100644 --- a/libs/libclkarchopenfpga/arch/example_internal_drivers.xml +++ b/libs/libclkarchopenfpga/arch/example_internal_drivers.xml @@ -1,6 +1,11 @@ + + + + + diff --git a/libs/libclkarchopenfpga/src/base/clock_network.cpp b/libs/libclkarchopenfpga/src/base/clock_network.cpp index e989e88f4..abeb4154e 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.cpp +++ b/libs/libclkarchopenfpga/src/base/clock_network.cpp @@ -270,6 +270,18 @@ vtr::Point ClockNetwork::spine_end_point( return spine_end_points_[spine_id]; } +std::vector ClockNetwork::spine_intermediate_drivers( + const ClockSpineId& spine_id, const vtr::Point& coord) const { + VTR_ASSERT(valid_spine_id(spine_id)); + /* Convert coord to a unique string */ + std::string coord_str = std::to_string(coord.x()) + std::string(",") + std::to_string(coord.y()); + auto result = spine_intermediate_drivers_[spine_id].find(coord_str); + if (result == spine_intermediate_drivers_[spine_id].end()) { + return std::vector(); + } + return result->second; +} + ClockLevelId ClockNetwork::spine_level(const ClockSpineId& spine_id) const { VTR_ASSERT(valid_spine_id(spine_id)); if (is_dirty_) { @@ -624,6 +636,7 @@ void ClockNetwork::reserve_spines(const size_t& num_spines) { spine_switch_points_.reserve(num_spines); spine_switch_coords_.reserve(num_spines); spine_switch_internal_drivers_.reserve(num_spines); + spine_intermediate_drivers_.reserve(num_spines); spine_parents_.reserve(num_spines); spine_children_.reserve(num_spines); spine_parent_trees_.reserve(num_spines); @@ -716,6 +729,7 @@ ClockSpineId ClockNetwork::create_spine(const std::string& name) { spine_switch_points_.emplace_back(); spine_switch_coords_.emplace_back(); spine_switch_internal_drivers_.emplace_back(); + spine_intermediate_drivers_.emplace_back(); spine_parents_.emplace_back(); spine_children_.emplace_back(); spine_parent_trees_.emplace_back(); @@ -817,6 +831,45 @@ ClockInternalDriverId ClockNetwork::add_spine_switch_point_internal_driver( return int_driver_id; } +ClockInternalDriverId ClockNetwork::add_spine_intermediate_driver( + const ClockSpineId& spine_id, const vtr::Point& coord, + const std::string& int_driver_from_port, + const std::string& int_driver_to_port) { + VTR_ASSERT(valid_spine_id(spine_id)); + /* Convert coord to a unique string */ + std::string coord_str = std::to_string(coord.x()) + std::string(",") + std::to_string(coord.y()); + /* Parse ports */ + PortParser to_pin_parser(int_driver_to_port); + /* Find any existing id for the driver port */ + ClockInternalDriverId int_driver_id_to_add = ClockInternalDriverId(internal_driver_ids_.size()); + for (ClockInternalDriverId int_driver_id : internal_driver_ids_) { + if (internal_driver_from_pins_[int_driver_id] == int_driver_from_port && + internal_driver_to_pins_[int_driver_id] == to_pin_parser.port()) { + int_driver_id_to_add = int_driver_id; + break; + } + } + /* Reaching here, no existing id can be reused, create a new one */ + if (int_driver_id_to_add == ClockInternalDriverId(internal_driver_ids_.size())) { + internal_driver_ids_.push_back(int_driver_id_to_add); + internal_driver_from_pins_.push_back(int_driver_from_port); + internal_driver_to_pins_.push_back(to_pin_parser.port()); + } + /* Add it to existing map, avoid duplicated id */ + auto result = spine_intermediate_drivers_[spine_id].find(coord_str); + if (result == spine_intermediate_drivers_[spine_id].end()) { + spine_intermediate_drivers_[spine_id][coord_str].push_back(int_driver_id_to_add); + } else { + if (std::find(result->second.begin(), result->second.end(), int_driver_id_to_add) == result->second.end()) { + result->second.push_back(int_driver_id_to_add); + } else { + VTR_LOG_WARN("Skip intermediate driver (from_port='%s', to_port='%s') at (%s) as it is duplicated in the clock architecture description file!\n", + int_driver_from_port.c_str(), int_driver_to_port.c_str(), coord_str.c_str()); + } + } + return int_driver_id_to_add; +} + ClockTapId ClockNetwork::add_tree_tap(const ClockTreeId& tree_id, const BasicPort& from_port, const std::string& to_port) { diff --git a/libs/libclkarchopenfpga/src/base/clock_network.h b/libs/libclkarchopenfpga/src/base/clock_network.h index 2f1a09592..6e6194cef 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.h +++ b/libs/libclkarchopenfpga/src/base/clock_network.h @@ -97,6 +97,8 @@ class ClockNetwork { std::string spine_name(const ClockSpineId& spine_id) const; vtr::Point spine_start_point(const ClockSpineId& spine_id) const; vtr::Point spine_end_point(const ClockSpineId& spine_id) const; + std::vector spine_intermediate_drivers(const ClockSpineId& spine_id, const vtr::Point& coord) const; + /* Return the level where the spine locates in the multi-layer clock tree * structure */ ClockLevelId spine_level(const ClockSpineId& spine_id) const; @@ -227,6 +229,10 @@ class ClockNetwork { const ClockSpineId& spine_id, const ClockSwitchPointId& switch_point_id, const std::string& internal_driver_from_port, const std::string& internal_driver_to_port); + ClockInternalDriverId add_spine_intermediate_driver( + const ClockSpineId& spine_id, const vtr::Point& coord, + const std::string& internal_driver_from_port, + const std::string& internal_driver_to_port); ClockTapId add_tree_tap(const ClockTreeId& tree_id, const BasicPort& from_port, const std::string& to_port); @@ -314,6 +320,7 @@ class ClockNetwork { vtr::vector>> spine_switch_coords_; vtr::vector>> spine_switch_internal_drivers_; + vtr::vector>> spine_intermediate_drivers_; vtr::vector spine_parents_; vtr::vector> spine_children_; vtr::vector spine_parent_trees_; diff --git a/libs/libclkarchopenfpga/src/io/clock_network_xml_constants.h b/libs/libclkarchopenfpga/src/io/clock_network_xml_constants.h index 65e828573..8dc4aac92 100644 --- a/libs/libclkarchopenfpga/src/io/clock_network_xml_constants.h +++ b/libs/libclkarchopenfpga/src/io/clock_network_xml_constants.h @@ -21,6 +21,12 @@ constexpr const char* XML_CLOCK_SPINE_ATTRIBUTE_END_X = "end_x"; constexpr const char* XML_CLOCK_SPINE_ATTRIBUTE_END_Y = "end_y"; constexpr const char* XML_CLOCK_SPINE_ATTRIBUTE_TYPE = "type"; constexpr const char* XML_CLOCK_SPINE_ATTRIBUTE_DIRECTION = "direction"; +constexpr const char* XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_NODE_NAME = "intermediate_driver"; +constexpr const char* XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_TAP_NODE_NAME = "tap"; +constexpr const char* XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_X = "x"; +constexpr const char* XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_Y = "y"; +constexpr const char* XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_FROM_PIN = "from_pin"; +constexpr const char* XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_TO_PIN = "to_pin"; constexpr const char* XML_CLOCK_SPINE_SWITCH_POINT_NODE_NAME = "switch_point"; constexpr const char* XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_NODE_NAME = "internal_driver"; diff --git a/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp b/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp index 46f74641d..32195274a 100644 --- a/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp +++ b/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp @@ -178,6 +178,32 @@ static void read_xml_clock_spine_switch_point_internal_driver( int_driver_to_port_name); } +/******************************************************************** + * Parse XML codes of a to an object of ClockNetwork + *******************************************************************/ +static void read_xml_clock_spine_intermediate_driver_tap( + pugi::xml_node& xml_int_driver, const pugiutil::loc_data& loc_data, + ClockNetwork& clk_ntwk, const ClockSpineId& spine_id, + const vtr::Point& spine_coord) { + if (!clk_ntwk.valid_spine_id(spine_id)) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_int_driver), + "Invalid id of a clock spine!\n"); + } + + std::string int_driver_from_port_name = + get_attribute( + xml_int_driver, + XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_FROM_PIN, loc_data) + .as_string(); + std::string int_driver_to_port_name = + get_attribute(xml_int_driver, + XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_TO_PIN, + loc_data) + .as_string(); + clk_ntwk.add_spine_intermediate_driver(spine_id, spine_coord, int_driver_from_port_name, + int_driver_to_port_name); +} + /******************************************************************** * Parse XML codes of a to an object of ClockNetwork *******************************************************************/ @@ -229,6 +255,38 @@ static void read_xml_clock_spine_switch_point( } } +/******************************************************************** + * Parse XML codes of a to an object of ClockNetwork + *******************************************************************/ +static void read_xml_clock_spine_intermediate_driver( + pugi::xml_node& xml_driver, const pugiutil::loc_data& loc_data, + ClockNetwork& clk_ntwk, const ClockSpineId& spine_id) { + if (!clk_ntwk.valid_spine_id(spine_id)) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_driver), + "Invalid id of a clock spine!\n"); + } + + int tap_x = get_attribute(xml_driver, + XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_X, loc_data) + .as_int(); + int tap_y = get_attribute(xml_driver, + XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_Y, loc_data) + .as_int(); + + /* Add internal drivers if possible */ + for (pugi::xml_node xml_int_driver : xml_driver.children()) { + /* Error out if the XML child has an invalid name! */ + if (xml_int_driver.name() == + std::string(XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_TAP_NODE_NAME)) { + read_xml_clock_spine_intermediate_driver_tap( + xml_int_driver, loc_data, clk_ntwk, spine_id, vtr::Point(tap_x, tap_y)); + } else { + bad_tag(xml_int_driver, loc_data, xml_driver, + {XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_TAP_NODE_NAME}); + } + } +} + /******************************************************************** * Convert string to the enumerate of model type *******************************************************************/ @@ -333,9 +391,14 @@ static void read_xml_clock_spine(pugi::xml_node& xml_spine, std::string(XML_CLOCK_SPINE_SWITCH_POINT_NODE_NAME)) { read_xml_clock_spine_switch_point(xml_switch_point, loc_data, clk_ntwk, spine_id); + } else if (xml_switch_point.name() == + std::string(XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_NODE_NAME)) { + read_xml_clock_spine_intermediate_driver(xml_switch_point, loc_data, clk_ntwk, + spine_id); + } else { bad_tag(xml_switch_point, loc_data, xml_spine, - {XML_CLOCK_SPINE_SWITCH_POINT_NODE_NAME}); + {XML_CLOCK_SPINE_SWITCH_POINT_NODE_NAME, XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_NODE_NAME}); } } } diff --git a/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp b/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp index 1d9937141..dfcdaa41d 100644 --- a/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp +++ b/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp @@ -142,6 +142,39 @@ static int write_xml_clock_spine_switch_point( return 0; } +static int write_xml_clock_spine_intermediate_drivers( + std::fstream& fp, const ClockNetwork& clk_ntwk, const ClockSpineId& spine_id, + const vtr::Point& coord) { + std::vector int_drivers = clk_ntwk.spine_intermediate_drivers(spine_id, coord); + if (int_drivers.empty()) { + return 0; + } + openfpga::write_tab_to_file(fp, 3); + fp << "<" << XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_NODE_NAME << ""; + + write_xml_attribute(fp, XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_X, coord.x()); + write_xml_attribute(fp, XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_Y, coord.y()); + + for (ClockInternalDriverId int_driver_id : int_drivers) { + openfpga::write_tab_to_file(fp, 4); + fp << "<" << XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_TAP_NODE_NAME; + write_xml_attribute( + fp, XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_FROM_PIN, + clk_ntwk.internal_driver_from_pin(int_driver_id).c_str()); + write_xml_attribute( + fp, XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_TO_PIN, + clk_ntwk.internal_driver_to_pin(int_driver_id) + .to_verilog_string() + .c_str()); + fp << "/>" + << "\n"; + } + fp << "\n"; + + return 0; +} + + static int write_xml_clock_spine(std::fstream& fp, const ClockNetwork& clk_ntwk, const ClockSpineId& spine_id) { openfpga::write_tab_to_file(fp, 2); @@ -166,6 +199,10 @@ static int write_xml_clock_spine(std::fstream& fp, const ClockNetwork& clk_ntwk, fp << ">" << "\n"; + for (const vtr::Point& coord : clk_ntwk.spine_coordinates(spine_id)) { + write_xml_clock_spine_intermediate_drivers(fp, clk_ntwk, spine_id, coord); + } + for (const ClockSwitchPointId& switch_point_id : clk_ntwk.spine_switch_points(spine_id)) { write_xml_clock_spine_switch_point(fp, clk_ntwk, spine_id, switch_point_id); From 1332d426c7f3d50875d690a551e703ba7dcabed6 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 20 Sep 2024 17:42:53 -0700 Subject: [PATCH 02/16] [core] code format --- .../src/base/clock_network.cpp | 25 ++++++++----- .../src/base/clock_network.h | 9 +++-- .../src/io/clock_network_xml_constants.h | 9 +++-- .../src/io/read_xml_clock_network.cpp | 36 ++++++++++--------- .../src/io/write_xml_clock_network.cpp | 20 ++++++----- 5 files changed, 60 insertions(+), 39 deletions(-) diff --git a/libs/libclkarchopenfpga/src/base/clock_network.cpp b/libs/libclkarchopenfpga/src/base/clock_network.cpp index abeb4154e..d70ed59a8 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.cpp +++ b/libs/libclkarchopenfpga/src/base/clock_network.cpp @@ -274,7 +274,8 @@ std::vector ClockNetwork::spine_intermediate_drivers( const ClockSpineId& spine_id, const vtr::Point& coord) const { VTR_ASSERT(valid_spine_id(spine_id)); /* Convert coord to a unique string */ - std::string coord_str = std::to_string(coord.x()) + std::string(",") + std::to_string(coord.y()); + std::string coord_str = + std::to_string(coord.x()) + std::string(",") + std::to_string(coord.y()); auto result = spine_intermediate_drivers_[spine_id].find(coord_str); if (result == spine_intermediate_drivers_[spine_id].end()) { return std::vector(); @@ -837,11 +838,13 @@ ClockInternalDriverId ClockNetwork::add_spine_intermediate_driver( const std::string& int_driver_to_port) { VTR_ASSERT(valid_spine_id(spine_id)); /* Convert coord to a unique string */ - std::string coord_str = std::to_string(coord.x()) + std::string(",") + std::to_string(coord.y()); + std::string coord_str = + std::to_string(coord.x()) + std::string(",") + std::to_string(coord.y()); /* Parse ports */ PortParser to_pin_parser(int_driver_to_port); /* Find any existing id for the driver port */ - ClockInternalDriverId int_driver_id_to_add = ClockInternalDriverId(internal_driver_ids_.size()); + ClockInternalDriverId int_driver_id_to_add = + ClockInternalDriverId(internal_driver_ids_.size()); for (ClockInternalDriverId int_driver_id : internal_driver_ids_) { if (internal_driver_from_pins_[int_driver_id] == int_driver_from_port && internal_driver_to_pins_[int_driver_id] == to_pin_parser.port()) { @@ -850,7 +853,8 @@ ClockInternalDriverId ClockNetwork::add_spine_intermediate_driver( } } /* Reaching here, no existing id can be reused, create a new one */ - if (int_driver_id_to_add == ClockInternalDriverId(internal_driver_ids_.size())) { + if (int_driver_id_to_add == + ClockInternalDriverId(internal_driver_ids_.size())) { internal_driver_ids_.push_back(int_driver_id_to_add); internal_driver_from_pins_.push_back(int_driver_from_port); internal_driver_to_pins_.push_back(to_pin_parser.port()); @@ -858,13 +862,18 @@ ClockInternalDriverId ClockNetwork::add_spine_intermediate_driver( /* Add it to existing map, avoid duplicated id */ auto result = spine_intermediate_drivers_[spine_id].find(coord_str); if (result == spine_intermediate_drivers_[spine_id].end()) { - spine_intermediate_drivers_[spine_id][coord_str].push_back(int_driver_id_to_add); + spine_intermediate_drivers_[spine_id][coord_str].push_back( + int_driver_id_to_add); } else { - if (std::find(result->second.begin(), result->second.end(), int_driver_id_to_add) == result->second.end()) { + if (std::find(result->second.begin(), result->second.end(), + int_driver_id_to_add) == result->second.end()) { result->second.push_back(int_driver_id_to_add); } else { - VTR_LOG_WARN("Skip intermediate driver (from_port='%s', to_port='%s') at (%s) as it is duplicated in the clock architecture description file!\n", - int_driver_from_port.c_str(), int_driver_to_port.c_str(), coord_str.c_str()); + VTR_LOG_WARN( + "Skip intermediate driver (from_port='%s', to_port='%s') at (%s) as it " + "is duplicated in the clock architecture description file!\n", + int_driver_from_port.c_str(), int_driver_to_port.c_str(), + coord_str.c_str()); } } return int_driver_id_to_add; diff --git a/libs/libclkarchopenfpga/src/base/clock_network.h b/libs/libclkarchopenfpga/src/base/clock_network.h index 6e6194cef..1ee5dabcc 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.h +++ b/libs/libclkarchopenfpga/src/base/clock_network.h @@ -97,8 +97,9 @@ class ClockNetwork { std::string spine_name(const ClockSpineId& spine_id) const; vtr::Point spine_start_point(const ClockSpineId& spine_id) const; vtr::Point spine_end_point(const ClockSpineId& spine_id) const; - std::vector spine_intermediate_drivers(const ClockSpineId& spine_id, const vtr::Point& coord) const; - + std::vector spine_intermediate_drivers( + const ClockSpineId& spine_id, const vtr::Point& coord) const; + /* Return the level where the spine locates in the multi-layer clock tree * structure */ ClockLevelId spine_level(const ClockSpineId& spine_id) const; @@ -320,7 +321,9 @@ class ClockNetwork { vtr::vector>> spine_switch_coords_; vtr::vector>> spine_switch_internal_drivers_; - vtr::vector>> spine_intermediate_drivers_; + vtr::vector>> + spine_intermediate_drivers_; vtr::vector spine_parents_; vtr::vector> spine_children_; vtr::vector spine_parent_trees_; diff --git a/libs/libclkarchopenfpga/src/io/clock_network_xml_constants.h b/libs/libclkarchopenfpga/src/io/clock_network_xml_constants.h index 8dc4aac92..2a1838c07 100644 --- a/libs/libclkarchopenfpga/src/io/clock_network_xml_constants.h +++ b/libs/libclkarchopenfpga/src/io/clock_network_xml_constants.h @@ -21,12 +21,15 @@ constexpr const char* XML_CLOCK_SPINE_ATTRIBUTE_END_X = "end_x"; constexpr const char* XML_CLOCK_SPINE_ATTRIBUTE_END_Y = "end_y"; constexpr const char* XML_CLOCK_SPINE_ATTRIBUTE_TYPE = "type"; constexpr const char* XML_CLOCK_SPINE_ATTRIBUTE_DIRECTION = "direction"; -constexpr const char* XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_NODE_NAME = "intermediate_driver"; +constexpr const char* XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_NODE_NAME = + "intermediate_driver"; constexpr const char* XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_TAP_NODE_NAME = "tap"; constexpr const char* XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_X = "x"; constexpr const char* XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_Y = "y"; -constexpr const char* XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_FROM_PIN = "from_pin"; -constexpr const char* XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_TO_PIN = "to_pin"; +constexpr const char* XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_FROM_PIN = + "from_pin"; +constexpr const char* XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_TO_PIN = + "to_pin"; constexpr const char* XML_CLOCK_SPINE_SWITCH_POINT_NODE_NAME = "switch_point"; constexpr const char* XML_CLOCK_SPINE_SWITCH_POINT_INTERNAL_DRIVER_NODE_NAME = "internal_driver"; diff --git a/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp b/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp index 32195274a..418e43611 100644 --- a/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp +++ b/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp @@ -191,17 +191,17 @@ static void read_xml_clock_spine_intermediate_driver_tap( } std::string int_driver_from_port_name = - get_attribute( - xml_int_driver, - XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_FROM_PIN, loc_data) + get_attribute(xml_int_driver, + XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_FROM_PIN, + loc_data) .as_string(); std::string int_driver_to_port_name = get_attribute(xml_int_driver, XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_TO_PIN, loc_data) .as_string(); - clk_ntwk.add_spine_intermediate_driver(spine_id, spine_coord, int_driver_from_port_name, - int_driver_to_port_name); + clk_ntwk.add_spine_intermediate_driver( + spine_id, spine_coord, int_driver_from_port_name, int_driver_to_port_name); } /******************************************************************** @@ -266,12 +266,14 @@ static void read_xml_clock_spine_intermediate_driver( "Invalid id of a clock spine!\n"); } - int tap_x = get_attribute(xml_driver, - XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_X, loc_data) - .as_int(); - int tap_y = get_attribute(xml_driver, - XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_Y, loc_data) - .as_int(); + int tap_x = + get_attribute(xml_driver, XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_X, + loc_data) + .as_int(); + int tap_y = + get_attribute(xml_driver, XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_Y, + loc_data) + .as_int(); /* Add internal drivers if possible */ for (pugi::xml_node xml_int_driver : xml_driver.children()) { @@ -279,7 +281,8 @@ static void read_xml_clock_spine_intermediate_driver( if (xml_int_driver.name() == std::string(XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_TAP_NODE_NAME)) { read_xml_clock_spine_intermediate_driver_tap( - xml_int_driver, loc_data, clk_ntwk, spine_id, vtr::Point(tap_x, tap_y)); + xml_int_driver, loc_data, clk_ntwk, spine_id, + vtr::Point(tap_x, tap_y)); } else { bad_tag(xml_int_driver, loc_data, xml_driver, {XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_TAP_NODE_NAME}); @@ -392,13 +395,14 @@ static void read_xml_clock_spine(pugi::xml_node& xml_spine, read_xml_clock_spine_switch_point(xml_switch_point, loc_data, clk_ntwk, spine_id); } else if (xml_switch_point.name() == - std::string(XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_NODE_NAME)) { - read_xml_clock_spine_intermediate_driver(xml_switch_point, loc_data, clk_ntwk, - spine_id); + std::string(XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_NODE_NAME)) { + read_xml_clock_spine_intermediate_driver(xml_switch_point, loc_data, + clk_ntwk, spine_id); } else { bad_tag(xml_switch_point, loc_data, xml_spine, - {XML_CLOCK_SPINE_SWITCH_POINT_NODE_NAME, XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_NODE_NAME}); + {XML_CLOCK_SPINE_SWITCH_POINT_NODE_NAME, + XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_NODE_NAME}); } } } diff --git a/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp b/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp index dfcdaa41d..23f54addf 100644 --- a/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp +++ b/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp @@ -145,15 +145,18 @@ static int write_xml_clock_spine_switch_point( static int write_xml_clock_spine_intermediate_drivers( std::fstream& fp, const ClockNetwork& clk_ntwk, const ClockSpineId& spine_id, const vtr::Point& coord) { - std::vector int_drivers = clk_ntwk.spine_intermediate_drivers(spine_id, coord); + std::vector int_drivers = + clk_ntwk.spine_intermediate_drivers(spine_id, coord); if (int_drivers.empty()) { return 0; } openfpga::write_tab_to_file(fp, 3); fp << "<" << XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_NODE_NAME << ""; - write_xml_attribute(fp, XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_X, coord.x()); - write_xml_attribute(fp, XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_Y, coord.y()); + write_xml_attribute(fp, XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_X, + coord.x()); + write_xml_attribute(fp, XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_Y, + coord.y()); for (ClockInternalDriverId int_driver_id : int_drivers) { openfpga::write_tab_to_file(fp, 4); @@ -161,11 +164,11 @@ static int write_xml_clock_spine_intermediate_drivers( write_xml_attribute( fp, XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_FROM_PIN, clk_ntwk.internal_driver_from_pin(int_driver_id).c_str()); - write_xml_attribute( - fp, XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_TO_PIN, - clk_ntwk.internal_driver_to_pin(int_driver_id) - .to_verilog_string() - .c_str()); + write_xml_attribute(fp, + XML_CLOCK_SPINE_INTERMEDIATE_DRIVER_ATTRIBUTE_TO_PIN, + clk_ntwk.internal_driver_to_pin(int_driver_id) + .to_verilog_string() + .c_str()); fp << "/>" << "\n"; } @@ -174,7 +177,6 @@ static int write_xml_clock_spine_intermediate_drivers( return 0; } - static int write_xml_clock_spine(std::fstream& fp, const ClockNetwork& clk_ntwk, const ClockSpineId& spine_id) { openfpga::write_tab_to_file(fp, 2); From e8957b6fd8a8d5f3fcc21b6b615d59e613a587e4 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 20 Sep 2024 19:07:16 -0700 Subject: [PATCH 03/16] [core] enable clock intermediate driver in rrgraph buildup --- .../src/annotation/append_clock_rr_graph.cpp | 76 +++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/openfpga/src/annotation/append_clock_rr_graph.cpp b/openfpga/src/annotation/append_clock_rr_graph.cpp index 56862ac91..cc9dbe60d 100644 --- a/openfpga/src/annotation/append_clock_rr_graph.cpp +++ b/openfpga/src/annotation/append_clock_rr_graph.cpp @@ -736,6 +736,79 @@ static int add_rr_graph_opin2clk_edges( return CMD_EXEC_SUCCESS; } +/******************************************************************** + * Add edges between OPIN of programmable blocks and clock routing tracks + * Note that such edges only occur at the intermeidate points of spines + * Different from add_rr_graph_opin2clk_edges(), we follow the clock spines + *here By expanding on intermediate points, internal drivers will be added + *******************************************************************/ +static int add_rr_graph_opin2clk_intermediate_edges( + RRGraphBuilder& rr_graph_builder, size_t& num_edges_to_create, + const RRClockSpatialLookup& clk_rr_lookup, const RRGraphView& rr_graph_view, + const DeviceGrid& grids, const size_t& layer, const ClockNetwork& clk_ntwk, + const bool& verbose) { + size_t edge_count = 0; + for (ClockTreeId clk_tree : clk_ntwk.trees()) { + for (ClockSpineId ispine : clk_ntwk.spines(clk_tree)) { + VTR_LOGV(verbose, "Finding internal drivers on spine '%s'...\n", + clk_ntwk.spine_name(ispine).c_str()); + for (auto ipin : clk_ntwk.pins(clk_tree)) { + for (const vtr::Point& coord : clk_ntwk.spine_coordinates(ispine)) { + if (clk_ntwk.spine_intermediate_drivers(ispine, coord).empty()) { + continue; + } + size_t curr_edge_count = edge_count; + /* Get the rr node of destination spine */ + Direction des_spine_direction = clk_ntwk.spine_direction(ispine); + ClockLevelId des_spine_level = clk_ntwk.spine_level(ispine); + vtr::Point des_coord; + /* des node depends on the type of routing track and direction. But it should be a starting point at the current SB[x][y] */ + if (des_spine_direction == Direction::INC && clk_ntwk.spine_track_type(ispine) == CHANX) { + des_coord.set_x(coord.x() + 1); + des_coord.set_y(coord.y()); + } + if (des_spine_direction == Direction::DEC && clk_ntwk.spine_track_type(ispine) == CHANX) { + des_coord.set_x(coord.x()); + des_coord.set_y(coord.y()); + } + if (des_spine_direction == Direction::INC && clk_ntwk.spine_track_type(ispine) == CHANY) { + des_coord.set_x(coord.x()); + des_coord.set_y(coord.y() + 1); + } + if (des_spine_direction == Direction::DEC && clk_ntwk.spine_track_type(ispine) == CHANY) { + des_coord.set_x(coord.x()); + des_coord.set_y(coord.y()); + } + RRNodeId des_node = clk_rr_lookup.find_node( + des_coord.x(), des_coord.y(), clk_tree, des_spine_level, ipin, + des_spine_direction, verbose); + if (!rr_graph_view.valid_node(des_node)) { + continue; + } + /* Walk through each qualified OPIN, build edges */ + std::vector int_driver_ids = clk_ntwk.spine_intermediate_drivers(ispine, coord); + for (RRNodeId src_node : find_clock_opin2track_node( + grids, rr_graph_view, layer, coord, clk_ntwk, ipin, + int_driver_ids, verbose)) { + /* Create edges */ + VTR_ASSERT(rr_graph_view.valid_node(des_node)); + rr_graph_builder.create_edge( + src_node, des_node, clk_ntwk.default_driver_switch(), false); + edge_count++; + } + VTR_LOGV(verbose, "\tWill add %lu edges from OPINs as intermediate drivers at (x=%lu, y=%lu)\n", + edge_count - curr_edge_count, des_coord.x(), des_coord.y()); + } + } + } + } + /* Allocate edges */ + rr_graph_builder.build_edges(true); + num_edges_to_create += edge_count; + return CMD_EXEC_SUCCESS; +} + + /******************************************************************** * Add edges to interconnect clock nodes * Walk through the routing tracks in each connection block (driver nodes) @@ -812,6 +885,9 @@ static void add_rr_graph_clock_edges( add_rr_graph_opin2clk_edges(rr_graph_builder, num_edges_to_create, clk_rr_lookup, rr_graph_view, grids, layer, clk_ntwk, verbose); + add_rr_graph_opin2clk_intermediate_edges(rr_graph_builder, num_edges_to_create, + clk_rr_lookup, rr_graph_view, grids, layer, + clk_ntwk, verbose); } /******************************************************************** From f87e095558996ce51f7972c89059b9a522d32ac7 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 20 Sep 2024 19:22:39 -0700 Subject: [PATCH 04/16] [core] support intermediate driver in clock routing --- .../src/annotation/append_clock_rr_graph.cpp | 12 +---- .../src/annotation/route_clock_rr_graph.cpp | 44 +++++++++++++++++++ 2 files changed, 45 insertions(+), 11 deletions(-) diff --git a/openfpga/src/annotation/append_clock_rr_graph.cpp b/openfpga/src/annotation/append_clock_rr_graph.cpp index cc9dbe60d..6fe98875c 100644 --- a/openfpga/src/annotation/append_clock_rr_graph.cpp +++ b/openfpga/src/annotation/append_clock_rr_graph.cpp @@ -761,24 +761,14 @@ static int add_rr_graph_opin2clk_intermediate_edges( /* Get the rr node of destination spine */ Direction des_spine_direction = clk_ntwk.spine_direction(ispine); ClockLevelId des_spine_level = clk_ntwk.spine_level(ispine); - vtr::Point des_coord; + vtr::Point des_coord(coord.x(), coord.y()); /* des node depends on the type of routing track and direction. But it should be a starting point at the current SB[x][y] */ if (des_spine_direction == Direction::INC && clk_ntwk.spine_track_type(ispine) == CHANX) { des_coord.set_x(coord.x() + 1); - des_coord.set_y(coord.y()); - } - if (des_spine_direction == Direction::DEC && clk_ntwk.spine_track_type(ispine) == CHANX) { - des_coord.set_x(coord.x()); - des_coord.set_y(coord.y()); } if (des_spine_direction == Direction::INC && clk_ntwk.spine_track_type(ispine) == CHANY) { - des_coord.set_x(coord.x()); des_coord.set_y(coord.y() + 1); } - if (des_spine_direction == Direction::DEC && clk_ntwk.spine_track_type(ispine) == CHANY) { - des_coord.set_x(coord.x()); - des_coord.set_y(coord.y()); - } RRNodeId des_node = clk_rr_lookup.find_node( des_coord.x(), des_coord.y(), clk_tree, des_spine_level, ipin, des_spine_direction, verbose); diff --git a/openfpga/src/annotation/route_clock_rr_graph.cpp b/openfpga/src/annotation/route_clock_rr_graph.cpp index 79cad9ecb..2ff70bfc5 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.cpp +++ b/openfpga/src/annotation/route_clock_rr_graph.cpp @@ -449,6 +449,50 @@ static int rec_expand_and_route_clock_spine( des_spine_direction, verbose); VTR_ASSERT(rr_graph.valid_node(src_node)); VTR_ASSERT(rr_graph.valid_node(des_node)); + + /* Internal drivers may appear at the intermediate. Check if there are + * any defined and related rr_node found as incoming edges. If the + * global net is mapped to the internal driver, use it as the previous + * node */ + size_t use_int_driver = 0; + if (!clk_ntwk.spine_intermediate_drivers(curr_spine, des_coord) + .empty() && + tree2clk_pin_map.find(curr_pin) != tree2clk_pin_map.end()) { + for (RREdgeId cand_edge : rr_graph.node_in_edges(des_node)) { + RRNodeId opin_node = rr_graph.edge_src_node(cand_edge); + if (OPIN != rr_graph.node_type(opin_node)) { + continue; + } + if (rr_node_gnets[opin_node] != tree2clk_pin_map.at(curr_pin)) { + continue; + } + /* This is the opin node we need, use it as the internal driver */ + vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node, + opin_node); + vpr_routing_annotation.set_rr_node_net(opin_node, + tree2clk_pin_map.at(curr_pin)); + vpr_routing_annotation.set_rr_node_net(des_node, + tree2clk_pin_map.at(curr_pin)); + use_int_driver++; + VTR_LOGV(verbose, + "Routed intermediate point of spine '%s' at " + "(%lu, %lu) using internal driver\n", + clk_ntwk.spine_name(curr_spine).c_str(), des_coord.x(), + des_coord.y()); + } + } + if (use_int_driver > 1) { + VTR_LOG_ERROR( + "Found %lu internal drivers for the intermediate point (%lu, %lu) for " + "spine '%s'!\n Expect only 1!\n", + use_int_driver, des_coord.x(), des_coord.y(), + clk_ntwk.spine_name(curr_spine).c_str()); + return CMD_EXEC_FATAL_ERROR; + } + if (use_int_driver == 1) { + continue; /* Used internal driver, early pass. */ + } + VTR_LOGV(verbose, "Routed backbone of spine '%s' from (x=%lu, y=%lu) to (x=%lu, " "y=%lu)...\n", From 2bb87ea278fc2d9b5fe77a917d77b5fcdb1cf7c6 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 20 Sep 2024 19:23:14 -0700 Subject: [PATCH 05/16] [core] code format --- .../src/annotation/append_clock_rr_graph.cpp | 30 +++++++++++-------- .../src/annotation/route_clock_rr_graph.cpp | 3 +- 2 files changed, 19 insertions(+), 14 deletions(-) diff --git a/openfpga/src/annotation/append_clock_rr_graph.cpp b/openfpga/src/annotation/append_clock_rr_graph.cpp index 6fe98875c..d118c38f1 100644 --- a/openfpga/src/annotation/append_clock_rr_graph.cpp +++ b/openfpga/src/annotation/append_clock_rr_graph.cpp @@ -753,7 +753,8 @@ static int add_rr_graph_opin2clk_intermediate_edges( VTR_LOGV(verbose, "Finding internal drivers on spine '%s'...\n", clk_ntwk.spine_name(ispine).c_str()); for (auto ipin : clk_ntwk.pins(clk_tree)) { - for (const vtr::Point& coord : clk_ntwk.spine_coordinates(ispine)) { + for (const vtr::Point& coord : + clk_ntwk.spine_coordinates(ispine)) { if (clk_ntwk.spine_intermediate_drivers(ispine, coord).empty()) { continue; } @@ -762,13 +763,16 @@ static int add_rr_graph_opin2clk_intermediate_edges( Direction des_spine_direction = clk_ntwk.spine_direction(ispine); ClockLevelId des_spine_level = clk_ntwk.spine_level(ispine); vtr::Point des_coord(coord.x(), coord.y()); - /* des node depends on the type of routing track and direction. But it should be a starting point at the current SB[x][y] */ - if (des_spine_direction == Direction::INC && clk_ntwk.spine_track_type(ispine) == CHANX) { + /* des node depends on the type of routing track and direction. But it + * should be a starting point at the current SB[x][y] */ + if (des_spine_direction == Direction::INC && + clk_ntwk.spine_track_type(ispine) == CHANX) { des_coord.set_x(coord.x() + 1); - } - if (des_spine_direction == Direction::INC && clk_ntwk.spine_track_type(ispine) == CHANY) { + } + if (des_spine_direction == Direction::INC && + clk_ntwk.spine_track_type(ispine) == CHANY) { des_coord.set_y(coord.y() + 1); - } + } RRNodeId des_node = clk_rr_lookup.find_node( des_coord.x(), des_coord.y(), clk_tree, des_spine_level, ipin, des_spine_direction, verbose); @@ -776,7 +780,8 @@ static int add_rr_graph_opin2clk_intermediate_edges( continue; } /* Walk through each qualified OPIN, build edges */ - std::vector int_driver_ids = clk_ntwk.spine_intermediate_drivers(ispine, coord); + std::vector int_driver_ids = + clk_ntwk.spine_intermediate_drivers(ispine, coord); for (RRNodeId src_node : find_clock_opin2track_node( grids, rr_graph_view, layer, coord, clk_ntwk, ipin, int_driver_ids, verbose)) { @@ -786,7 +791,9 @@ static int add_rr_graph_opin2clk_intermediate_edges( src_node, des_node, clk_ntwk.default_driver_switch(), false); edge_count++; } - VTR_LOGV(verbose, "\tWill add %lu edges from OPINs as intermediate drivers at (x=%lu, y=%lu)\n", + VTR_LOGV(verbose, + "\tWill add %lu edges from OPINs as intermediate drivers at " + "(x=%lu, y=%lu)\n", edge_count - curr_edge_count, des_coord.x(), des_coord.y()); } } @@ -798,7 +805,6 @@ static int add_rr_graph_opin2clk_intermediate_edges( return CMD_EXEC_SUCCESS; } - /******************************************************************** * Add edges to interconnect clock nodes * Walk through the routing tracks in each connection block (driver nodes) @@ -875,9 +881,9 @@ static void add_rr_graph_clock_edges( add_rr_graph_opin2clk_edges(rr_graph_builder, num_edges_to_create, clk_rr_lookup, rr_graph_view, grids, layer, clk_ntwk, verbose); - add_rr_graph_opin2clk_intermediate_edges(rr_graph_builder, num_edges_to_create, - clk_rr_lookup, rr_graph_view, grids, layer, - clk_ntwk, verbose); + add_rr_graph_opin2clk_intermediate_edges( + rr_graph_builder, num_edges_to_create, clk_rr_lookup, rr_graph_view, grids, + layer, clk_ntwk, verbose); } /******************************************************************** diff --git a/openfpga/src/annotation/route_clock_rr_graph.cpp b/openfpga/src/annotation/route_clock_rr_graph.cpp index 2ff70bfc5..fd4ae69b9 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.cpp +++ b/openfpga/src/annotation/route_clock_rr_graph.cpp @@ -455,8 +455,7 @@ static int rec_expand_and_route_clock_spine( * global net is mapped to the internal driver, use it as the previous * node */ size_t use_int_driver = 0; - if (!clk_ntwk.spine_intermediate_drivers(curr_spine, des_coord) - .empty() && + if (!clk_ntwk.spine_intermediate_drivers(curr_spine, des_coord).empty() && tree2clk_pin_map.find(curr_pin) != tree2clk_pin_map.end()) { for (RREdgeId cand_edge : rr_graph.node_in_edges(des_node)) { RRNodeId opin_node = rr_graph.edge_src_node(cand_edge); From ed33b62a60c696df3c88feafe9175f6eae121d7d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 20 Sep 2024 19:27:40 -0700 Subject: [PATCH 06/16] [test] add new tests to validate intermediate drivers in clock --- .../regression_test_scripts/basic_reg_test.sh | 1 + ...k_arch_1clk_1rst_2layer_int_driver_clk.xml | 37 ++++++++++++ ...k_arch_1clk_1rst_2layer_int_driver_rst.xml | 35 ++++++++++++ .../config/pin_constraints_clk_cond.xml | 9 +++ .../config/pin_constraints_rst_cond.xml | 8 +++ .../config/repack_pin_constraints.xml | 4 ++ .../config/task.conf | 57 +++++++++++++++++++ .../config/vpr_constraint_clk_cond.xml | 12 ++++ .../config/vpr_constraint_rst_cond.xml | 12 ++++ 9 files changed, 175 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/clk_arch_1clk_1rst_2layer_int_driver_clk.xml create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/clk_arch_1clk_1rst_2layer_int_driver_rst.xml create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/pin_constraints_clk_cond.xml create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/pin_constraints_rst_cond.xml create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/repack_pin_constraints.xml create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/task.conf create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/vpr_constraint_clk_cond.xml create mode 100644 openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/vpr_constraint_rst_cond.xml diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index c75e4634d..e5dd8fa57 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -262,6 +262,7 @@ run-task basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup run-task basic_tests/clock_network/homo_1clock_1reset_2layer_syntax $@ run-task basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines $@ run-task basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver $@ +run-task basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver $@ echo -e "Testing configuration chain of a K4N4 FPGA using .blif generated by yosys+verific"; run-task basic_tests/verific_test $@ diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/clk_arch_1clk_1rst_2layer_int_driver_clk.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/clk_arch_1clk_1rst_2layer_int_driver_clk.xml new file mode 100644 index 000000000..270ca7f33 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/clk_arch_1clk_1rst_2layer_int_driver_clk.xml @@ -0,0 +1,37 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/clk_arch_1clk_1rst_2layer_int_driver_rst.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/clk_arch_1clk_1rst_2layer_int_driver_rst.xml new file mode 100644 index 000000000..b0f8d5333 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/clk_arch_1clk_1rst_2layer_int_driver_rst.xml @@ -0,0 +1,35 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/pin_constraints_clk_cond.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/pin_constraints_clk_cond.xml new file mode 100644 index 000000000..903c4bfac --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/pin_constraints_clk_cond.xml @@ -0,0 +1,9 @@ + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/pin_constraints_rst_cond.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/pin_constraints_rst_cond.xml new file mode 100644 index 000000000..55e49733f --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/pin_constraints_rst_cond.xml @@ -0,0 +1,8 @@ + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/repack_pin_constraints.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/repack_pin_constraints.xml new file mode 100644 index 000000000..06a125111 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/repack_pin_constraints.xml @@ -0,0 +1,4 @@ + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/task.conf new file mode 100644 index 000000000..a4841a1ae --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/task.conf @@ -0,0 +1,57 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 3*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_clkntwk_int_driver_no_ace_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_Ntwk1clk1rst2lvl_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml +openfpga_vpr_device_layout=2x2 +openfpga_vpr_route_chan_width=32 +openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer_int_driver.xml +openfpga_verilog_testbench_port_mapping=--explicit_port_mapping +openfpga_route_clock_options= +openfpga_vpr_constraint_file=${PATH:TASK_DIR}/config/vpr_constraint_clk_cond.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/clk_cond/clk_cond.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/rst_cond/rst_cond.v + +[SYNTHESIS_PARAM] +# Yosys script parameters +bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v +bench_yosys_dff_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v +bench_read_verilog_options_common = -nolatches +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys +bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys + +bench0_top = clk_cond +bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_clk_cond.xml +bench0_openfpga_vpr_constraint_file=${PATH:TASK_DIR}/config/vpr_constraint_clk_cond.xml +bench0_openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer_int_driver_clk.xml + +bench1_top = rst_cond +bench1_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_rst_cond.xml +bench1_openfpga_vpr_constraint_file=${PATH:TASK_DIR}/config/vpr_constraint_rst_cond.xml +bench1_openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer_int_driver_rst.xml + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/vpr_constraint_clk_cond.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/vpr_constraint_clk_cond.xml new file mode 100644 index 000000000..f9b30b022 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/vpr_constraint_clk_cond.xml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/vpr_constraint_rst_cond.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/vpr_constraint_rst_cond.xml new file mode 100644 index 000000000..3c6f27aef --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/vpr_constraint_rst_cond.xml @@ -0,0 +1,12 @@ + + + + + + + + + + + + From 6d3d36626e3c350181bd5a47e432fe188cd287c2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 20 Sep 2024 19:29:47 -0700 Subject: [PATCH 07/16] [test] typo --- .../config/clk_arch_1clk_1rst_2layer_int_driver_rst.xml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/clk_arch_1clk_1rst_2layer_int_driver_rst.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/clk_arch_1clk_1rst_2layer_int_driver_rst.xml index b0f8d5333..d2df1756d 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/clk_arch_1clk_1rst_2layer_int_driver_rst.xml +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/clk_arch_1clk_1rst_2layer_int_driver_rst.xml @@ -17,10 +17,10 @@ - + - - + + From 6551ca81e54cf5782b781e313d76edcd9bc0a833 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 20 Sep 2024 19:48:02 -0700 Subject: [PATCH 08/16] [core] debugging --- .../src/annotation/route_clock_rr_graph.cpp | 46 +++++++++++++++++++ .../config/vpr_constraint_clk_cond.xml | 4 +- .../config/vpr_constraint_rst_cond.xml | 2 +- 3 files changed, 49 insertions(+), 3 deletions(-) diff --git a/openfpga/src/annotation/route_clock_rr_graph.cpp b/openfpga/src/annotation/route_clock_rr_graph.cpp index fd4ae69b9..e60da7fb3 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.cpp +++ b/openfpga/src/annotation/route_clock_rr_graph.cpp @@ -427,6 +427,52 @@ static int rec_expand_and_route_clock_spine( * The skip condition may cause this. */ /* Skip the first stop */ if (icoord == spine_coords.size() - 1) { + vtr::Point des_coord = spine_coords[icoord]; + Direction des_spine_direction = clk_ntwk.spine_direction(curr_spine); + ClockLevelId des_spine_level = clk_ntwk.spine_level(curr_spine); + RRNodeId des_node = clk_rr_lookup.find_node( + des_coord.x(), des_coord.y(), clk_tree, des_spine_level, curr_pin, + des_spine_direction, verbose); + VTR_ASSERT(rr_graph.valid_node(des_node)); + + /* Internal drivers may appear at the intermediate. Check if there are + * any defined and related rr_node found as incoming edges. If the + * global net is mapped to the internal driver, use it as the previous + * node */ + size_t use_int_driver = 0; + if (!clk_ntwk.spine_intermediate_drivers(curr_spine, des_coord).empty() && + tree2clk_pin_map.find(curr_pin) != tree2clk_pin_map.end()) { + for (RREdgeId cand_edge : rr_graph.node_in_edges(des_node)) { + RRNodeId opin_node = rr_graph.edge_src_node(cand_edge); + if (OPIN != rr_graph.node_type(opin_node)) { + continue; + } + if (rr_node_gnets[opin_node] != tree2clk_pin_map.at(curr_pin)) { + continue; + } + /* This is the opin node we need, use it as the internal driver */ + vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node, + opin_node); + vpr_routing_annotation.set_rr_node_net(opin_node, + tree2clk_pin_map.at(curr_pin)); + vpr_routing_annotation.set_rr_node_net(des_node, + tree2clk_pin_map.at(curr_pin)); + use_int_driver++; + VTR_LOGV(verbose, + "Routed intermediate point of spine '%s' at " + "(%lu, %lu) using internal driver\n", + clk_ntwk.spine_name(curr_spine).c_str(), des_coord.x(), + des_coord.y()); + } + } + if (use_int_driver > 1) { + VTR_LOG_ERROR( + "Found %lu internal drivers for the intermediate point (%lu, %lu) for " + "spine '%s'!\n Expect only 1!\n", + use_int_driver, des_coord.x(), des_coord.y(), + clk_ntwk.spine_name(curr_spine).c_str()); + return CMD_EXEC_FATAL_ERROR; + } continue; } /* Connect only when next stop is used */ diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/vpr_constraint_clk_cond.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/vpr_constraint_clk_cond.xml index f9b30b022..b80e7299c 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/vpr_constraint_clk_cond.xml +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/vpr_constraint_clk_cond.xml @@ -2,11 +2,11 @@ - + - + diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/vpr_constraint_rst_cond.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/vpr_constraint_rst_cond.xml index 3c6f27aef..8ae00e08f 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/vpr_constraint_rst_cond.xml +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/vpr_constraint_rst_cond.xml @@ -2,7 +2,7 @@ - + From 33a253da3dcd72a16670375e11192e1e0195cb3e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 20 Sep 2024 22:20:41 -0700 Subject: [PATCH 09/16] [core] fixed the bug --- .../src/annotation/route_clock_rr_graph.cpp | 28 +++++++++++++++++-- .../config/vpr_constraint_clk_cond.xml | 2 +- 2 files changed, 27 insertions(+), 3 deletions(-) diff --git a/openfpga/src/annotation/route_clock_rr_graph.cpp b/openfpga/src/annotation/route_clock_rr_graph.cpp index e60da7fb3..fe5e6a9fc 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.cpp +++ b/openfpga/src/annotation/route_clock_rr_graph.cpp @@ -440,8 +440,20 @@ static int rec_expand_and_route_clock_spine( * global net is mapped to the internal driver, use it as the previous * node */ size_t use_int_driver = 0; - if (!clk_ntwk.spine_intermediate_drivers(curr_spine, des_coord).empty() && + vtr::Point int_driver_coord(des_coord.x(), des_coord.y()); + if (des_spine_direction == Direction::INC && + clk_ntwk.spine_track_type(curr_spine) == CHANX) { + int_driver_coord.set_x(des_coord.x() - 1); + } + if (des_spine_direction == Direction::INC && + clk_ntwk.spine_track_type(curr_spine) == CHANY) { + int_driver_coord.set_y(des_coord.y() - 1); + } + + if (!clk_ntwk.spine_intermediate_drivers(curr_spine, int_driver_coord).empty() && tree2clk_pin_map.find(curr_pin) != tree2clk_pin_map.end()) { + VTR_LOGV(verbose, "Finding intermediate drivers at (%d, %d) for spine '%s'\n", + des_coord.x(), des_coord.y(), clk_ntwk.spine_name(curr_spine).c_str()); for (RREdgeId cand_edge : rr_graph.node_in_edges(des_node)) { RRNodeId opin_node = rr_graph.edge_src_node(cand_edge); if (OPIN != rr_graph.node_type(opin_node)) { @@ -501,8 +513,20 @@ static int rec_expand_and_route_clock_spine( * global net is mapped to the internal driver, use it as the previous * node */ size_t use_int_driver = 0; - if (!clk_ntwk.spine_intermediate_drivers(curr_spine, des_coord).empty() && + vtr::Point int_driver_coord(des_coord.x(), des_coord.y()); + if (des_spine_direction == Direction::INC && + clk_ntwk.spine_track_type(curr_spine) == CHANX) { + int_driver_coord.set_x(des_coord.x() - 1); + } + if (des_spine_direction == Direction::INC && + clk_ntwk.spine_track_type(curr_spine) == CHANY) { + int_driver_coord.set_y(des_coord.y() - 1); + } + + if (!clk_ntwk.spine_intermediate_drivers(curr_spine, int_driver_coord).empty() && tree2clk_pin_map.find(curr_pin) != tree2clk_pin_map.end()) { + VTR_LOGV(verbose, "Finding intermediate drivers at (%d, %d) for spine '%s'\n", + des_coord.x(), des_coord.y(), clk_ntwk.spine_name(curr_spine).c_str()); for (RREdgeId cand_edge : rr_graph.node_in_edges(des_node)) { RRNodeId opin_node = rr_graph.edge_src_node(cand_edge); if (OPIN != rr_graph.node_type(opin_node)) { diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/vpr_constraint_clk_cond.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/vpr_constraint_clk_cond.xml index b80e7299c..f7a7dccd5 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/vpr_constraint_clk_cond.xml +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver/config/vpr_constraint_clk_cond.xml @@ -6,7 +6,7 @@ - + From 4e85a6f4145614bcac63e08fc6faf7ae0e1c213c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 20 Sep 2024 22:37:05 -0700 Subject: [PATCH 10/16] [core] code format --- .../src/annotation/route_clock_rr_graph.cpp | 20 ++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/openfpga/src/annotation/route_clock_rr_graph.cpp b/openfpga/src/annotation/route_clock_rr_graph.cpp index fe5e6a9fc..428dddc12 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.cpp +++ b/openfpga/src/annotation/route_clock_rr_graph.cpp @@ -450,10 +450,13 @@ static int rec_expand_and_route_clock_spine( int_driver_coord.set_y(des_coord.y() - 1); } - if (!clk_ntwk.spine_intermediate_drivers(curr_spine, int_driver_coord).empty() && + if (!clk_ntwk.spine_intermediate_drivers(curr_spine, int_driver_coord) + .empty() && tree2clk_pin_map.find(curr_pin) != tree2clk_pin_map.end()) { - VTR_LOGV(verbose, "Finding intermediate drivers at (%d, %d) for spine '%s'\n", - des_coord.x(), des_coord.y(), clk_ntwk.spine_name(curr_spine).c_str()); + VTR_LOGV(verbose, + "Finding intermediate drivers at (%d, %d) for spine '%s'\n", + des_coord.x(), des_coord.y(), + clk_ntwk.spine_name(curr_spine).c_str()); for (RREdgeId cand_edge : rr_graph.node_in_edges(des_node)) { RRNodeId opin_node = rr_graph.edge_src_node(cand_edge); if (OPIN != rr_graph.node_type(opin_node)) { @@ -479,7 +482,8 @@ static int rec_expand_and_route_clock_spine( } if (use_int_driver > 1) { VTR_LOG_ERROR( - "Found %lu internal drivers for the intermediate point (%lu, %lu) for " + "Found %lu internal drivers for the intermediate point (%lu, %lu) " + "for " "spine '%s'!\n Expect only 1!\n", use_int_driver, des_coord.x(), des_coord.y(), clk_ntwk.spine_name(curr_spine).c_str()); @@ -523,10 +527,12 @@ static int rec_expand_and_route_clock_spine( int_driver_coord.set_y(des_coord.y() - 1); } - if (!clk_ntwk.spine_intermediate_drivers(curr_spine, int_driver_coord).empty() && + if (!clk_ntwk.spine_intermediate_drivers(curr_spine, int_driver_coord) + .empty() && tree2clk_pin_map.find(curr_pin) != tree2clk_pin_map.end()) { - VTR_LOGV(verbose, "Finding intermediate drivers at (%d, %d) for spine '%s'\n", - des_coord.x(), des_coord.y(), clk_ntwk.spine_name(curr_spine).c_str()); + VTR_LOGV( + verbose, "Finding intermediate drivers at (%d, %d) for spine '%s'\n", + des_coord.x(), des_coord.y(), clk_ntwk.spine_name(curr_spine).c_str()); for (RREdgeId cand_edge : rr_graph.node_in_edges(des_node)) { RRNodeId opin_node = rr_graph.edge_src_node(cand_edge); if (OPIN != rr_graph.node_type(opin_node)) { From 26cda624d30f26a32d26d788721ab4d2b5890d61 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 21 Sep 2024 13:31:30 -0700 Subject: [PATCH 11/16] [doc] add new syntax about clock network --- .../manual/file_formats/clock_network.rst | 56 +++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/docs/source/manual/file_formats/clock_network.rst b/docs/source/manual/file_formats/clock_network.rst index 62e266347..1f075a3d4 100644 --- a/docs/source/manual/file_formats/clock_network.rst +++ b/docs/source/manual/file_formats/clock_network.rst @@ -27,6 +27,9 @@ The entry point of a clock tree must be at a valid connection block. + + + @@ -179,6 +182,59 @@ where a horizental clock spine ``spine0`` is defined which spans from (1, 1) to .. note:: We only support clock spines in horizental and vertical directions. Diagonal clock spine is not supported! +.. _file_formats_clock_network_intermediate_driver: + +Intermediate Driver +^^^^^^^^^^^^^^^^^^^ + +The following syntax are applicable to the XML definition tagged by ``intermediate_driver`` +Note that a number of intermediate drivers can be defined under each clock spine ``spine``. + +.. option:: x="" + + The coordinate X where the intermediate driver should occur on the spine. Must be a valid coordinate within the range of the current clock spine and the clock spine to be tapped. + +.. option:: y="" + + The coordinate Y where the intermediate driver should occur on the spine. Must be a valid coordinate within the range of the current clock spine and the clock spine to be tapped. + +.. note:: The intermeidate driver is different than the internal driver (see details in :ref:`file_formats_clock_network_switch_point`). Intermediate driver may occur in any mid points of a spine, while internal driver occurs **ONLY** on the switch points between spines. + +Under each intermediate driver, a number of tap points can be specified. +For each tap point, outputs of neighbouring programmable blocks are allowed to drive the spine through syntax ``tap``. + +.. option:: from_pin="" + + Define the pin of a programmable block as an internal driver to a clock network. The pin must be a valid pin defined in the VPR architecture description file. + +.. option:: to_pin="" + + Define the source pin of a clock network. The pin must be a valid pin of the global ports defined in the tile_annotation part of OpenFPGA architecture description file. + +For example, + +.. code-block:: xml + + + + + + + + + + +where the clock routing can be driven at (x=1,y=1) by the output pins ``O[0:3]`` of tile ``clb`` in a VPR architecture description file: + +.. code-block:: xml + + + + + + + + .. _file_formats_clock_network_switch_point: Switch Point Settings From af09120a521161a461de3d65d96b6802002b46de Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 21 Sep 2024 13:35:42 -0700 Subject: [PATCH 12/16] [doc] update fig --- .../manual/file_formats/clock_network.rst | 5 ++++- ...g_clk_network_example_2x2_perimeter_cb.png | Bin 82100 -> 74048 bytes 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/docs/source/manual/file_formats/clock_network.rst b/docs/source/manual/file_formats/clock_network.rst index 1f075a3d4..c1fa9c695 100644 --- a/docs/source/manual/file_formats/clock_network.rst +++ b/docs/source/manual/file_formats/clock_network.rst @@ -224,7 +224,10 @@ For example, -where the clock routing can be driven at (x=1,y=1) by the output pins ``O[0:3]`` of tile ``clb`` in a VPR architecture description file: + +where clock spine ``spine0`` will be driven by other programmable blocks at (1, 1), as highlighted in purple in the :numref:`fig_prog_clock_network_example_2x2_perimeter_cb` + +To be specific, the clock routing can be driven at (x=1,y=1) by the output pins ``O[0:3]`` of tile ``clb`` in a VPR architecture description file: .. code-block:: xml diff --git a/docs/source/manual/file_formats/figures/prog_clk_network_example_2x2_perimeter_cb.png b/docs/source/manual/file_formats/figures/prog_clk_network_example_2x2_perimeter_cb.png index e74ded94f30eeec1f701efa94d2872c34670cada..4ec057d1c12d34e2b40f6a655445d9e1c656fec2 100644 GIT binary patch literal 74048 zcmeFZbyStz7B36}(hU;QNGTww#HPDLK)MA5!A&=8klb`D2uOp{ASK=1NJ%%F?iRQY z_!{py?|0An=eyti?zm&GuWU;I1;H#e|1|wqcj$)gm(i!OAJ;lQccG!@p|?2rfX&a35259$6htZAT%WKA zv#gskugI{-fxIYxQEELA%$)P0!;Dr_Bh|;48NES>-TFwftI=gH37dvXyNA|_Or)Kwld%rTIS7B3dvDnLZ zg(eaGp!5j zW|gz!{s~Ee=EZ7_{)6jhQdh8?Hbe`+M>AF#=XyO-Gv##fH%1$JRN`~%@%_PL#smGU zv(cz}X2Z`8GpF0;SldoZYl_!XN#WIvY=iI9+>(r z1%~v}IDH!=9i(WNCaPwO5}{__5A#=CoQxPI6Dd(8A3O$23*Gp)6hoYqEsYk^C#~g1 zbC=wO1B&xX6*(mIM68FLDhK3an#1!qk#r0sB!7s+$+KaGMctW=MM}OK5Xb9Lz5bfZ zktS~~yw+0o){PvWUND+@Rv`Wmys`zA$NmDepRBlu3z{NZO$8SFoBi*z#rPfYGrZajFt%IFUB)rfyOCYV26^_QQ4QH@ z+VcPGfqdWr-M=0%xx!S>cjp=D3KO6ZT;SNcG!yz06^uyBcoDTL_gDlXf%dQ zO%%qxxIo3=!Vl$jgVzv=o~$@-{2FhWbZD#Xw09v`%i>sj7{CSYqKv&aEg(z#rx~Mf z*#`VDqm%>``r#9Nfo{kTn0bCPv|TZeNn9w)!~N5-G(@ojKO}g<(|HYq2-}qbLAQ&t z$JmfrsOi2t9^j6m;(-S~@=lzb_905_?_u*GmoSIq}LP{V)XFClp`7C^c)KHLtx>;tc3 z8OhL-;~9^-iI+^#?H^pXDooHFC#|6q7XGde`5@X`ZtM7#HWO%$Gmzu8$2G@iU-o-> z)hDKGx>&Z(js6UZroFfDTfRY#r$+hq+G%@K6#0kwE)Krt2<~npAY*-*Kq;Sc(BAJC z#m*boqHsT%OKZt4&wE3oRMt>i%}K%d=0z1Ug;PEF@$J=fI)y=F4&)M}HmvfVNJc}u zS*KR(?_)+`c{ZrC+uRaRdT=av7dz&L80N-I-OQ9)|Ebfcu44t5@4&%`Ato+^lw6~Q zn&*6@c#2cjFn?0GmyE~mlk;v1(L~}@_DYh6`&&_B%j!*R3cj&2H_fZVb@kU>A4HQp zBv%B&lTu^!T(XKkEbX>YT9%u|H9@hfz^zn&1c-heB>HZD>YANK^bfZYF(L?3-n1Zg z#-|%T%0&9wQnuTl6jJAU{fPe8dz(Wlin{V%4dO()i)AFY&T&$>kH<9>cvjP2j^^v; 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But it + * should be a starting point at the current SB[x][y] */ + if (des_spine_direction == Direction::INC && + spine_track_type(spine_id) == CHANX) { + des_coord.set_x(coord.x() + 1); + } + if (des_spine_direction == Direction::INC && + spine_track_type(spine_id) == CHANY) { + des_coord.set_y(coord.y() + 1); + } + return des_coord; +} + +std::vector ClockNetwork::spine_intermediate_drivers_by_routing_track( + const ClockSpineId& spine_id, const vtr::Point& track_coord) const { + vtr::Point des_coord(track_coord.x(), track_coord.y()); + Direction des_spine_direction = spine_direction(spine_id); + /* des node depends on the type of routing track and direction. But it + * should be a starting point at the current SB[x][y] */ + if (des_spine_direction == Direction::INC && + spine_track_type(spine_id) == CHANX) { + des_coord.set_x(track_coord.x() - 1); + } + if (des_spine_direction == Direction::INC && + spine_track_type(spine_id) == CHANY) { + des_coord.set_y(track_coord.y() - 1); + } + return spine_intermediate_drivers(spine_id, des_coord); +} + ClockLevelId ClockNetwork::spine_level(const ClockSpineId& spine_id) const { VTR_ASSERT(valid_spine_id(spine_id)); if (is_dirty_) { diff --git a/libs/libclkarchopenfpga/src/base/clock_network.h b/libs/libclkarchopenfpga/src/base/clock_network.h index 1ee5dabcc..494d17220 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.h +++ b/libs/libclkarchopenfpga/src/base/clock_network.h @@ -97,8 +97,14 @@ class ClockNetwork { std::string spine_name(const ClockSpineId& spine_id) const; vtr::Point spine_start_point(const ClockSpineId& spine_id) const; vtr::Point spine_end_point(const ClockSpineId& spine_id) const; + /* Find the intermediate drivers by the SB coordinate */ std::vector spine_intermediate_drivers( const ClockSpineId& spine_id, const vtr::Point& coord) const; + /* Find the coordinate of routing track which the intermediate driver will driver. Note that the coordinate may be different than the coordinate of intermeidate driver. One of the exceptions lies in the CHANX with INC direction, which starts actually on the routing tracks on the right side of a SB, resulting in x -> x + 1. Another exception is on the CHANY with INC direction, which starts actually on the routing tracks on the top side of a SB, resulting in y - > y + 1. This function is to provide an official conversion the coordinates. */ + vtr::Point spine_intermediate_driver_routing_track_coord(const ClockSpineId& spine_id, const vtr::Point& coord) const; + /* Find the intermediate drivers by the routing track starting point. Note that the routing track starting point may be different from the SB coordinate. See the exceptions in the spine_intermediate_driver_track_coord() */ + std::vector spine_intermediate_drivers_by_routing_track( + const ClockSpineId& spine_id, const vtr::Point& track_coord) const; /* Return the level where the spine locates in the multi-layer clock tree * structure */ @@ -273,7 +279,6 @@ class ClockNetwork { /* Validate the internal data. Required to ensure clean data before usage. If * validation is successful, is_valid() will return true */ bool validate() const; - private: /* Public invalidators/validators */ /* Ensure tree data is clean. All the spines are valid, and switch points are * valid */ diff --git a/openfpga/src/annotation/append_clock_rr_graph.cpp b/openfpga/src/annotation/append_clock_rr_graph.cpp index d118c38f1..f45480b00 100644 --- a/openfpga/src/annotation/append_clock_rr_graph.cpp +++ b/openfpga/src/annotation/append_clock_rr_graph.cpp @@ -762,17 +762,7 @@ static int add_rr_graph_opin2clk_intermediate_edges( /* Get the rr node of destination spine */ Direction des_spine_direction = clk_ntwk.spine_direction(ispine); ClockLevelId des_spine_level = clk_ntwk.spine_level(ispine); - vtr::Point des_coord(coord.x(), coord.y()); - /* des node depends on the type of routing track and direction. But it - * should be a starting point at the current SB[x][y] */ - if (des_spine_direction == Direction::INC && - clk_ntwk.spine_track_type(ispine) == CHANX) { - des_coord.set_x(coord.x() + 1); - } - if (des_spine_direction == Direction::INC && - clk_ntwk.spine_track_type(ispine) == CHANY) { - des_coord.set_y(coord.y() + 1); - } + vtr::Point des_coord = clk_ntwk.spine_intermediate_driver_routing_track_coord(ispine, coord); RRNodeId des_node = clk_rr_lookup.find_node( des_coord.x(), des_coord.y(), clk_tree, des_spine_level, ipin, des_spine_direction, verbose); diff --git a/openfpga/src/annotation/route_clock_rr_graph.cpp b/openfpga/src/annotation/route_clock_rr_graph.cpp index 428dddc12..78f32eb65 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.cpp +++ b/openfpga/src/annotation/route_clock_rr_graph.cpp @@ -440,17 +440,7 @@ static int rec_expand_and_route_clock_spine( * global net is mapped to the internal driver, use it as the previous * node */ size_t use_int_driver = 0; - vtr::Point int_driver_coord(des_coord.x(), des_coord.y()); - if (des_spine_direction == Direction::INC && - clk_ntwk.spine_track_type(curr_spine) == CHANX) { - int_driver_coord.set_x(des_coord.x() - 1); - } - if (des_spine_direction == Direction::INC && - clk_ntwk.spine_track_type(curr_spine) == CHANY) { - int_driver_coord.set_y(des_coord.y() - 1); - } - - if (!clk_ntwk.spine_intermediate_drivers(curr_spine, int_driver_coord) + if (!clk_ntwk.spine_intermediate_drivers_by_routing_track(curr_spine, des_coord) .empty() && tree2clk_pin_map.find(curr_pin) != tree2clk_pin_map.end()) { VTR_LOGV(verbose, @@ -517,17 +507,7 @@ static int rec_expand_and_route_clock_spine( * global net is mapped to the internal driver, use it as the previous * node */ size_t use_int_driver = 0; - vtr::Point int_driver_coord(des_coord.x(), des_coord.y()); - if (des_spine_direction == Direction::INC && - clk_ntwk.spine_track_type(curr_spine) == CHANX) { - int_driver_coord.set_x(des_coord.x() - 1); - } - if (des_spine_direction == Direction::INC && - clk_ntwk.spine_track_type(curr_spine) == CHANY) { - int_driver_coord.set_y(des_coord.y() - 1); - } - - if (!clk_ntwk.spine_intermediate_drivers(curr_spine, int_driver_coord) + if (!clk_ntwk.spine_intermediate_drivers_by_routing_track(curr_spine, des_coord) .empty() && tree2clk_pin_map.find(curr_pin) != tree2clk_pin_map.end()) { VTR_LOGV( From 415fd9a8fa9d89c2cd8868e908abf1f210edc367 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 21 Sep 2024 21:39:30 -0700 Subject: [PATCH 14/16] [core] code format --- .../src/base/clock_network.cpp | 10 +++++---- .../src/base/clock_network.h | 21 +++++++++++++++---- .../src/annotation/append_clock_rr_graph.cpp | 4 +++- .../src/annotation/route_clock_rr_graph.cpp | 6 ++++-- 4 files changed, 30 insertions(+), 11 deletions(-) diff --git a/libs/libclkarchopenfpga/src/base/clock_network.cpp b/libs/libclkarchopenfpga/src/base/clock_network.cpp index 7c11c4541..a1c16709c 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.cpp +++ b/libs/libclkarchopenfpga/src/base/clock_network.cpp @@ -283,7 +283,8 @@ std::vector ClockNetwork::spine_intermediate_drivers( return result->second; } -vtr::Point ClockNetwork::spine_intermediate_driver_routing_track_coord(const ClockSpineId& spine_id, const vtr::Point& coord) const { +vtr::Point ClockNetwork::spine_intermediate_driver_routing_track_coord( + const ClockSpineId& spine_id, const vtr::Point& coord) const { vtr::Point des_coord(coord.x(), coord.y()); Direction des_spine_direction = spine_direction(spine_id); /* des node depends on the type of routing track and direction. But it @@ -299,8 +300,9 @@ vtr::Point ClockNetwork::spine_intermediate_driver_routing_track_coord(cons return des_coord; } -std::vector ClockNetwork::spine_intermediate_drivers_by_routing_track( - const ClockSpineId& spine_id, const vtr::Point& track_coord) const { +std::vector +ClockNetwork::spine_intermediate_drivers_by_routing_track( + const ClockSpineId& spine_id, const vtr::Point& track_coord) const { vtr::Point des_coord(track_coord.x(), track_coord.y()); Direction des_spine_direction = spine_direction(spine_id); /* des node depends on the type of routing track and direction. But it @@ -313,7 +315,7 @@ std::vector ClockNetwork::spine_intermediate_drivers_by_r spine_track_type(spine_id) == CHANY) { des_coord.set_y(track_coord.y() - 1); } - return spine_intermediate_drivers(spine_id, des_coord); + return spine_intermediate_drivers(spine_id, des_coord); } ClockLevelId ClockNetwork::spine_level(const ClockSpineId& spine_id) const { diff --git a/libs/libclkarchopenfpga/src/base/clock_network.h b/libs/libclkarchopenfpga/src/base/clock_network.h index 494d17220..9f7fe0fcb 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.h +++ b/libs/libclkarchopenfpga/src/base/clock_network.h @@ -100,10 +100,22 @@ class ClockNetwork { /* Find the intermediate drivers by the SB coordinate */ std::vector spine_intermediate_drivers( const ClockSpineId& spine_id, const vtr::Point& coord) const; - /* Find the coordinate of routing track which the intermediate driver will driver. Note that the coordinate may be different than the coordinate of intermeidate driver. One of the exceptions lies in the CHANX with INC direction, which starts actually on the routing tracks on the right side of a SB, resulting in x -> x + 1. Another exception is on the CHANY with INC direction, which starts actually on the routing tracks on the top side of a SB, resulting in y - > y + 1. This function is to provide an official conversion the coordinates. */ - vtr::Point spine_intermediate_driver_routing_track_coord(const ClockSpineId& spine_id, const vtr::Point& coord) const; - /* Find the intermediate drivers by the routing track starting point. Note that the routing track starting point may be different from the SB coordinate. See the exceptions in the spine_intermediate_driver_track_coord() */ - std::vector spine_intermediate_drivers_by_routing_track( + /* Find the coordinate of routing track which the intermediate driver will + * driver. Note that the coordinate may be different than the coordinate of + * intermeidate driver. One of the exceptions lies in the CHANX with INC + * direction, which starts actually on the routing tracks on the right side of + * a SB, resulting in x -> x + 1. Another exception is on the CHANY with INC + * direction, which starts actually on the routing tracks on the top side of a + * SB, resulting in y - > y + 1. This function is to provide an official + * conversion the coordinates. */ + vtr::Point spine_intermediate_driver_routing_track_coord( + const ClockSpineId& spine_id, const vtr::Point& coord) const; + /* Find the intermediate drivers by the routing track starting point. Note + * that the routing track starting point may be different from the SB + * coordinate. See the exceptions in the + * spine_intermediate_driver_track_coord() */ + std::vector + spine_intermediate_drivers_by_routing_track( const ClockSpineId& spine_id, const vtr::Point& track_coord) const; /* Return the level where the spine locates in the multi-layer clock tree @@ -279,6 +291,7 @@ class ClockNetwork { /* Validate the internal data. Required to ensure clean data before usage. If * validation is successful, is_valid() will return true */ bool validate() const; + private: /* Public invalidators/validators */ /* Ensure tree data is clean. All the spines are valid, and switch points are * valid */ diff --git a/openfpga/src/annotation/append_clock_rr_graph.cpp b/openfpga/src/annotation/append_clock_rr_graph.cpp index f45480b00..87ee34b41 100644 --- a/openfpga/src/annotation/append_clock_rr_graph.cpp +++ b/openfpga/src/annotation/append_clock_rr_graph.cpp @@ -762,7 +762,9 @@ static int add_rr_graph_opin2clk_intermediate_edges( /* Get the rr node of destination spine */ Direction des_spine_direction = clk_ntwk.spine_direction(ispine); ClockLevelId des_spine_level = clk_ntwk.spine_level(ispine); - vtr::Point des_coord = clk_ntwk.spine_intermediate_driver_routing_track_coord(ispine, coord); + vtr::Point des_coord = + clk_ntwk.spine_intermediate_driver_routing_track_coord(ispine, + coord); RRNodeId des_node = clk_rr_lookup.find_node( des_coord.x(), des_coord.y(), clk_tree, des_spine_level, ipin, des_spine_direction, verbose); diff --git a/openfpga/src/annotation/route_clock_rr_graph.cpp b/openfpga/src/annotation/route_clock_rr_graph.cpp index 78f32eb65..3ad73ecc4 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.cpp +++ b/openfpga/src/annotation/route_clock_rr_graph.cpp @@ -440,7 +440,8 @@ static int rec_expand_and_route_clock_spine( * global net is mapped to the internal driver, use it as the previous * node */ size_t use_int_driver = 0; - if (!clk_ntwk.spine_intermediate_drivers_by_routing_track(curr_spine, des_coord) + if (!clk_ntwk + .spine_intermediate_drivers_by_routing_track(curr_spine, des_coord) .empty() && tree2clk_pin_map.find(curr_pin) != tree2clk_pin_map.end()) { VTR_LOGV(verbose, @@ -507,7 +508,8 @@ static int rec_expand_and_route_clock_spine( * global net is mapped to the internal driver, use it as the previous * node */ size_t use_int_driver = 0; - if (!clk_ntwk.spine_intermediate_drivers_by_routing_track(curr_spine, des_coord) + if (!clk_ntwk + .spine_intermediate_drivers_by_routing_track(curr_spine, des_coord) .empty() && tree2clk_pin_map.find(curr_pin) != tree2clk_pin_map.end()) { VTR_LOGV( From f009180bbf473b95c1445f81bed51775222c19b1 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 21 Sep 2024 21:53:53 -0700 Subject: [PATCH 15/16] [core] refactor --- .../src/annotation/route_clock_rr_graph.cpp | 160 ++++++++---------- 1 file changed, 74 insertions(+), 86 deletions(-) diff --git a/openfpga/src/annotation/route_clock_rr_graph.cpp b/openfpga/src/annotation/route_clock_rr_graph.cpp index 3ad73ecc4..a697ec534 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.cpp +++ b/openfpga/src/annotation/route_clock_rr_graph.cpp @@ -293,6 +293,72 @@ static int route_spine_taps( return CMD_EXEC_SUCCESS; } + +/******************************************************************** + * Recursively route a clock spine on an existing routing resource graph + *******************************************************************/ +static int route_spine_intermediate_drivers( + VprRoutingAnnotation& vpr_routing_annotation, + const RRGraphView& rr_graph, const RRClockSpatialLookup& clk_rr_lookup, + const vtr::vector& rr_node_gnets, + const std::map& tree2clk_pin_map, + const ClockNetwork& clk_ntwk, const ClockTreeId& clk_tree, + const ClockSpineId& curr_spine, const ClockTreePinId& curr_pin, + const vtr::Point& des_coord, const bool& verbose) { + Direction des_spine_direction = clk_ntwk.spine_direction(curr_spine); + ClockLevelId des_spine_level = clk_ntwk.spine_level(curr_spine); + RRNodeId des_node = clk_rr_lookup.find_node( + des_coord.x(), des_coord.y(), clk_tree, des_spine_level, curr_pin, + des_spine_direction, verbose); + VTR_ASSERT(rr_graph.valid_node(des_node)); + + /* Internal drivers may appear at the intermediate. Check if there are + * any defined and related rr_node found as incoming edges. If the + * global net is mapped to the internal driver, use it as the previous + * node */ + size_t use_int_driver = 0; + if (!clk_ntwk + .spine_intermediate_drivers_by_routing_track(curr_spine, des_coord) + .empty() && + tree2clk_pin_map.find(curr_pin) != tree2clk_pin_map.end()) { + VTR_LOGV(verbose, + "Finding intermediate drivers at (%d, %d) for spine '%s'\n", + des_coord.x(), des_coord.y(), + clk_ntwk.spine_name(curr_spine).c_str()); + for (RREdgeId cand_edge : rr_graph.node_in_edges(des_node)) { + RRNodeId opin_node = rr_graph.edge_src_node(cand_edge); + if (OPIN != rr_graph.node_type(opin_node)) { + continue; + } + if (rr_node_gnets[opin_node] != tree2clk_pin_map.at(curr_pin)) { + continue; + } + /* This is the opin node we need, use it as the internal driver */ + vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node, + opin_node); + vpr_routing_annotation.set_rr_node_net(opin_node, + tree2clk_pin_map.at(curr_pin)); + vpr_routing_annotation.set_rr_node_net(des_node, + tree2clk_pin_map.at(curr_pin)); + use_int_driver++; + VTR_LOGV(verbose, + "Routed intermediate point of spine '%s' at " + "(%lu, %lu) using internal driver\n", + clk_ntwk.spine_name(curr_spine).c_str(), des_coord.x(), + des_coord.y()); + } + } + if (use_int_driver > 1) { + VTR_LOG_ERROR( + "Found %lu internal drivers for the intermediate point (%lu, %lu) " + "for " + "spine '%s'!\n Expect only 1!\n", + use_int_driver, des_coord.x(), des_coord.y(), + clk_ntwk.spine_name(curr_spine).c_str()); + } + return use_int_driver; +} + /******************************************************************** * Recursively route a clock spine on an existing routing resource graph * The strategy is to route spine one by one @@ -428,58 +494,13 @@ static int rec_expand_and_route_clock_spine( /* Skip the first stop */ if (icoord == spine_coords.size() - 1) { vtr::Point des_coord = spine_coords[icoord]; - Direction des_spine_direction = clk_ntwk.spine_direction(curr_spine); - ClockLevelId des_spine_level = clk_ntwk.spine_level(curr_spine); - RRNodeId des_node = clk_rr_lookup.find_node( - des_coord.x(), des_coord.y(), clk_tree, des_spine_level, curr_pin, - des_spine_direction, verbose); - VTR_ASSERT(rr_graph.valid_node(des_node)); - /* Internal drivers may appear at the intermediate. Check if there are - * any defined and related rr_node found as incoming edges. If the - * global net is mapped to the internal driver, use it as the previous - * node */ - size_t use_int_driver = 0; - if (!clk_ntwk - .spine_intermediate_drivers_by_routing_track(curr_spine, des_coord) - .empty() && - tree2clk_pin_map.find(curr_pin) != tree2clk_pin_map.end()) { - VTR_LOGV(verbose, - "Finding intermediate drivers at (%d, %d) for spine '%s'\n", - des_coord.x(), des_coord.y(), - clk_ntwk.spine_name(curr_spine).c_str()); - for (RREdgeId cand_edge : rr_graph.node_in_edges(des_node)) { - RRNodeId opin_node = rr_graph.edge_src_node(cand_edge); - if (OPIN != rr_graph.node_type(opin_node)) { - continue; - } - if (rr_node_gnets[opin_node] != tree2clk_pin_map.at(curr_pin)) { - continue; - } - /* This is the opin node we need, use it as the internal driver */ - vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node, - opin_node); - vpr_routing_annotation.set_rr_node_net(opin_node, - tree2clk_pin_map.at(curr_pin)); - vpr_routing_annotation.set_rr_node_net(des_node, - tree2clk_pin_map.at(curr_pin)); - use_int_driver++; - VTR_LOGV(verbose, - "Routed intermediate point of spine '%s' at " - "(%lu, %lu) using internal driver\n", - clk_ntwk.spine_name(curr_spine).c_str(), des_coord.x(), - des_coord.y()); - } - } + int use_int_driver = route_spine_intermediate_drivers(vpr_routing_annotation, + rr_graph, clk_rr_lookup, rr_node_gnets, tree2clk_pin_map, + clk_ntwk, clk_tree, curr_spine, curr_pin, des_coord, verbose); if (use_int_driver > 1) { - VTR_LOG_ERROR( - "Found %lu internal drivers for the intermediate point (%lu, %lu) " - "for " - "spine '%s'!\n Expect only 1!\n", - use_int_driver, des_coord.x(), des_coord.y(), - clk_ntwk.spine_name(curr_spine).c_str()); return CMD_EXEC_FATAL_ERROR; - } + } continue; } /* Connect only when next stop is used */ @@ -507,45 +528,12 @@ static int rec_expand_and_route_clock_spine( * any defined and related rr_node found as incoming edges. If the * global net is mapped to the internal driver, use it as the previous * node */ - size_t use_int_driver = 0; - if (!clk_ntwk - .spine_intermediate_drivers_by_routing_track(curr_spine, des_coord) - .empty() && - tree2clk_pin_map.find(curr_pin) != tree2clk_pin_map.end()) { - VTR_LOGV( - verbose, "Finding intermediate drivers at (%d, %d) for spine '%s'\n", - des_coord.x(), des_coord.y(), clk_ntwk.spine_name(curr_spine).c_str()); - for (RREdgeId cand_edge : rr_graph.node_in_edges(des_node)) { - RRNodeId opin_node = rr_graph.edge_src_node(cand_edge); - if (OPIN != rr_graph.node_type(opin_node)) { - continue; - } - if (rr_node_gnets[opin_node] != tree2clk_pin_map.at(curr_pin)) { - continue; - } - /* This is the opin node we need, use it as the internal driver */ - vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node, - opin_node); - vpr_routing_annotation.set_rr_node_net(opin_node, - tree2clk_pin_map.at(curr_pin)); - vpr_routing_annotation.set_rr_node_net(des_node, - tree2clk_pin_map.at(curr_pin)); - use_int_driver++; - VTR_LOGV(verbose, - "Routed intermediate point of spine '%s' at " - "(%lu, %lu) using internal driver\n", - clk_ntwk.spine_name(curr_spine).c_str(), des_coord.x(), - des_coord.y()); - } - } + int use_int_driver = route_spine_intermediate_drivers(vpr_routing_annotation, + rr_graph, clk_rr_lookup, rr_node_gnets, tree2clk_pin_map, + clk_ntwk, clk_tree, curr_spine, curr_pin, des_coord, verbose); if (use_int_driver > 1) { - VTR_LOG_ERROR( - "Found %lu internal drivers for the intermediate point (%lu, %lu) for " - "spine '%s'!\n Expect only 1!\n", - use_int_driver, des_coord.x(), des_coord.y(), - clk_ntwk.spine_name(curr_spine).c_str()); return CMD_EXEC_FATAL_ERROR; - } + } if (use_int_driver == 1) { continue; /* Used internal driver, early pass. */ } From c52610959c6304de76ac94efdf18a3564a40c27c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 21 Sep 2024 21:54:37 -0700 Subject: [PATCH 16/16] [core] code format --- .../src/annotation/route_clock_rr_graph.cpp | 30 +++++++++---------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/openfpga/src/annotation/route_clock_rr_graph.cpp b/openfpga/src/annotation/route_clock_rr_graph.cpp index a697ec534..55e096566 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.cpp +++ b/openfpga/src/annotation/route_clock_rr_graph.cpp @@ -293,13 +293,12 @@ static int route_spine_taps( return CMD_EXEC_SUCCESS; } - /******************************************************************** * Recursively route a clock spine on an existing routing resource graph *******************************************************************/ static int route_spine_intermediate_drivers( - VprRoutingAnnotation& vpr_routing_annotation, - const RRGraphView& rr_graph, const RRClockSpatialLookup& clk_rr_lookup, + VprRoutingAnnotation& vpr_routing_annotation, const RRGraphView& rr_graph, + const RRClockSpatialLookup& clk_rr_lookup, const vtr::vector& rr_node_gnets, const std::map& tree2clk_pin_map, const ClockNetwork& clk_ntwk, const ClockTreeId& clk_tree, @@ -321,10 +320,9 @@ static int route_spine_intermediate_drivers( .spine_intermediate_drivers_by_routing_track(curr_spine, des_coord) .empty() && tree2clk_pin_map.find(curr_pin) != tree2clk_pin_map.end()) { - VTR_LOGV(verbose, - "Finding intermediate drivers at (%d, %d) for spine '%s'\n", - des_coord.x(), des_coord.y(), - clk_ntwk.spine_name(curr_spine).c_str()); + VTR_LOGV( + verbose, "Finding intermediate drivers at (%d, %d) for spine '%s'\n", + des_coord.x(), des_coord.y(), clk_ntwk.spine_name(curr_spine).c_str()); for (RREdgeId cand_edge : rr_graph.node_in_edges(des_node)) { RRNodeId opin_node = rr_graph.edge_src_node(cand_edge); if (OPIN != rr_graph.node_type(opin_node)) { @@ -495,12 +493,13 @@ static int rec_expand_and_route_clock_spine( if (icoord == spine_coords.size() - 1) { vtr::Point des_coord = spine_coords[icoord]; - int use_int_driver = route_spine_intermediate_drivers(vpr_routing_annotation, - rr_graph, clk_rr_lookup, rr_node_gnets, tree2clk_pin_map, - clk_ntwk, clk_tree, curr_spine, curr_pin, des_coord, verbose); + int use_int_driver = route_spine_intermediate_drivers( + vpr_routing_annotation, rr_graph, clk_rr_lookup, rr_node_gnets, + tree2clk_pin_map, clk_ntwk, clk_tree, curr_spine, curr_pin, des_coord, + verbose); if (use_int_driver > 1) { return CMD_EXEC_FATAL_ERROR; - } + } continue; } /* Connect only when next stop is used */ @@ -528,12 +527,13 @@ static int rec_expand_and_route_clock_spine( * any defined and related rr_node found as incoming edges. If the * global net is mapped to the internal driver, use it as the previous * node */ - int use_int_driver = route_spine_intermediate_drivers(vpr_routing_annotation, - rr_graph, clk_rr_lookup, rr_node_gnets, tree2clk_pin_map, - clk_ntwk, clk_tree, curr_spine, curr_pin, des_coord, verbose); + int use_int_driver = route_spine_intermediate_drivers( + vpr_routing_annotation, rr_graph, clk_rr_lookup, rr_node_gnets, + tree2clk_pin_map, clk_ntwk, clk_tree, curr_spine, curr_pin, des_coord, + verbose); if (use_int_driver > 1) { return CMD_EXEC_FATAL_ERROR; - } + } if (use_int_driver == 1) { continue; /* Used internal driver, early pass. */ }