Fixed run test file
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@ -23,7 +23,7 @@ python3.5 openfpga_flow/scripts/run_fpga_flow.py \
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--fpga_flow vpr_blif \
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--fpga_flow vpr_blif \
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--top_module test_modes \
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--top_module test_modes \
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--activity_file ./openfpga_flow/benchmarks/Test_Modes/test_modes.act \
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--activity_file ./openfpga_flow/benchmarks/Test_Modes/test_modes.act \
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--base_verilog ./openfpga_flow/benchmarks/Test_Modes/test_modes.v\
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--base_verilog ./openfpga_flow/benchmarks/Test_Modes/test_modes.v \
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--power \
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--power \
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--power_tech ./openfpga_flow/tech/PTM_45nm/45nm.xml \
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--power_tech ./openfpga_flow/tech/PTM_45nm/45nm.xml \
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--fix_route_chan_width 300 \
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--fix_route_chan_width 300 \
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