From 417d534121197ca93b05d21a421062bf88855aac Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 23 Apr 2020 16:15:45 -0600
Subject: [PATCH] fine tune mcnc example script to run Modelsim simulations
 easily

---
 .../OpenFPGAShellScripts/mcnc_example_script.openfpga       | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga
index 66b4c12fa..9a4f577f8 100644
--- a/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga
@@ -37,7 +37,11 @@ build_fabric_bitstream --verbose
 
 # Write the Verilog netlist for FPGA fabric
 #  - Enable the use of explicit port mapping in Verilog netlist
-write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
+write_fabric_verilog --file ./SRC \
+  --explicit_port_mapping \
+  --include_timing \
+  --include_signal_init 
+  #--support_icarus_simulator 
 
 # Write the Verilog testbench for FPGA fabric
 #  - We suggest the use of same output directory as fabric Verilog netlists