diff --git a/libs/libclkarchopenfpga/src/base/clock_network.cpp b/libs/libclkarchopenfpga/src/base/clock_network.cpp
index 7c11c4541..a1c16709c 100644
--- a/libs/libclkarchopenfpga/src/base/clock_network.cpp
+++ b/libs/libclkarchopenfpga/src/base/clock_network.cpp
@@ -283,7 +283,8 @@ std::vector<ClockInternalDriverId> ClockNetwork::spine_intermediate_drivers(
   return result->second;
 }
 
-vtr::Point<int> ClockNetwork::spine_intermediate_driver_routing_track_coord(const ClockSpineId& spine_id, const vtr::Point<int>& coord) const {
+vtr::Point<int> ClockNetwork::spine_intermediate_driver_routing_track_coord(
+  const ClockSpineId& spine_id, const vtr::Point<int>& coord) const {
   vtr::Point<int> des_coord(coord.x(), coord.y());
   Direction des_spine_direction = spine_direction(spine_id);
   /* des node depends on the type of routing track and direction. But it
@@ -299,8 +300,9 @@ vtr::Point<int> ClockNetwork::spine_intermediate_driver_routing_track_coord(cons
   return des_coord;
 }
 
-std::vector<ClockInternalDriverId> ClockNetwork::spine_intermediate_drivers_by_routing_track(
-    const ClockSpineId& spine_id, const vtr::Point<int>& track_coord) const {
+std::vector<ClockInternalDriverId>
+ClockNetwork::spine_intermediate_drivers_by_routing_track(
+  const ClockSpineId& spine_id, const vtr::Point<int>& track_coord) const {
   vtr::Point<int> des_coord(track_coord.x(), track_coord.y());
   Direction des_spine_direction = spine_direction(spine_id);
   /* des node depends on the type of routing track and direction. But it
@@ -313,7 +315,7 @@ std::vector<ClockInternalDriverId> ClockNetwork::spine_intermediate_drivers_by_r
       spine_track_type(spine_id) == CHANY) {
     des_coord.set_y(track_coord.y() - 1);
   }
-  return spine_intermediate_drivers(spine_id, des_coord); 
+  return spine_intermediate_drivers(spine_id, des_coord);
 }
 
 ClockLevelId ClockNetwork::spine_level(const ClockSpineId& spine_id) const {
diff --git a/libs/libclkarchopenfpga/src/base/clock_network.h b/libs/libclkarchopenfpga/src/base/clock_network.h
index 494d17220..9f7fe0fcb 100644
--- a/libs/libclkarchopenfpga/src/base/clock_network.h
+++ b/libs/libclkarchopenfpga/src/base/clock_network.h
@@ -100,10 +100,22 @@ class ClockNetwork {
   /* Find the intermediate drivers by the SB coordinate */
   std::vector<ClockInternalDriverId> spine_intermediate_drivers(
     const ClockSpineId& spine_id, const vtr::Point<int>& coord) const;
-  /* Find the coordinate of routing track which the intermediate driver will driver. Note that the coordinate may be different than the coordinate of intermeidate driver. One of the exceptions lies in the CHANX with INC direction, which starts actually on the routing tracks on the right side of a SB, resulting in x -> x + 1. Another exception is on the CHANY with INC direction, which starts actually on the routing tracks on the top side of a SB, resulting in y - > y + 1. This function is to provide an official conversion the coordinates. */
-  vtr::Point<int> spine_intermediate_driver_routing_track_coord(const ClockSpineId& spine_id, const vtr::Point<int>& coord) const;
-  /* Find the intermediate drivers by the routing track starting point. Note that the routing track starting point may be different from the SB coordinate. See the exceptions in the spine_intermediate_driver_track_coord() */
-  std::vector<ClockInternalDriverId> spine_intermediate_drivers_by_routing_track(
+  /* Find the coordinate of routing track which the intermediate driver will
+   * driver. Note that the coordinate may be different than the coordinate of
+   * intermeidate driver. One of the exceptions lies in the CHANX with INC
+   * direction, which starts actually on the routing tracks on the right side of
+   * a SB, resulting in x -> x + 1. Another exception is on the CHANY with INC
+   * direction, which starts actually on the routing tracks on the top side of a
+   * SB, resulting in y - > y + 1. This function is to provide an official
+   * conversion the coordinates. */
+  vtr::Point<int> spine_intermediate_driver_routing_track_coord(
+    const ClockSpineId& spine_id, const vtr::Point<int>& coord) const;
+  /* Find the intermediate drivers by the routing track starting point. Note
+   * that the routing track starting point may be different from the SB
+   * coordinate. See the exceptions in the
+   * spine_intermediate_driver_track_coord() */
+  std::vector<ClockInternalDriverId>
+  spine_intermediate_drivers_by_routing_track(
     const ClockSpineId& spine_id, const vtr::Point<int>& track_coord) const;
 
   /* Return the level where the spine locates in the multi-layer clock tree
@@ -279,6 +291,7 @@ class ClockNetwork {
   /* Validate the internal data. Required to ensure clean data before usage. If
    * validation is successful, is_valid() will return true */
   bool validate() const;
+
  private: /* Public invalidators/validators */
   /* Ensure tree data is clean. All the spines are valid, and switch points are
    * valid */
diff --git a/openfpga/src/annotation/append_clock_rr_graph.cpp b/openfpga/src/annotation/append_clock_rr_graph.cpp
index f45480b00..87ee34b41 100644
--- a/openfpga/src/annotation/append_clock_rr_graph.cpp
+++ b/openfpga/src/annotation/append_clock_rr_graph.cpp
@@ -762,7 +762,9 @@ static int add_rr_graph_opin2clk_intermediate_edges(
           /* Get the rr node of destination spine */
           Direction des_spine_direction = clk_ntwk.spine_direction(ispine);
           ClockLevelId des_spine_level = clk_ntwk.spine_level(ispine);
-          vtr::Point<int> des_coord = clk_ntwk.spine_intermediate_driver_routing_track_coord(ispine, coord);
+          vtr::Point<int> des_coord =
+            clk_ntwk.spine_intermediate_driver_routing_track_coord(ispine,
+                                                                   coord);
           RRNodeId des_node = clk_rr_lookup.find_node(
             des_coord.x(), des_coord.y(), clk_tree, des_spine_level, ipin,
             des_spine_direction, verbose);
diff --git a/openfpga/src/annotation/route_clock_rr_graph.cpp b/openfpga/src/annotation/route_clock_rr_graph.cpp
index 78f32eb65..3ad73ecc4 100644
--- a/openfpga/src/annotation/route_clock_rr_graph.cpp
+++ b/openfpga/src/annotation/route_clock_rr_graph.cpp
@@ -440,7 +440,8 @@ static int rec_expand_and_route_clock_spine(
        * global net is mapped to the internal driver, use it as the previous
        * node  */
       size_t use_int_driver = 0;
-      if (!clk_ntwk.spine_intermediate_drivers_by_routing_track(curr_spine, des_coord)
+      if (!clk_ntwk
+             .spine_intermediate_drivers_by_routing_track(curr_spine, des_coord)
              .empty() &&
           tree2clk_pin_map.find(curr_pin) != tree2clk_pin_map.end()) {
         VTR_LOGV(verbose,
@@ -507,7 +508,8 @@ static int rec_expand_and_route_clock_spine(
      * global net is mapped to the internal driver, use it as the previous
      * node  */
     size_t use_int_driver = 0;
-    if (!clk_ntwk.spine_intermediate_drivers_by_routing_track(curr_spine, des_coord)
+    if (!clk_ntwk
+           .spine_intermediate_drivers_by_routing_track(curr_spine, des_coord)
            .empty() &&
         tree2clk_pin_map.find(curr_pin) != tree2clk_pin_map.end()) {
       VTR_LOGV(