Added external_fabric_key_file key
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c1b73efa62
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@ -85,6 +85,8 @@ parser.add_argument('--openfpga_arch_file', type=str,
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help="Openfpga architecture file for shell")
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parser.add_argument('--openfpga_sim_setting_file', type=str,
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help="Openfpga simulation file for shell")
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parser.add_argument('--external_fabric_key_file', type=str,
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help="Key file for shell")
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parser.add_argument('--yosys_tmpl', type=str,
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help="Alternate yosys template, generates top_module.blif")
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parser.add_argument('--disp', action="store_true",
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@ -686,6 +688,7 @@ def run_openfpga_shell():
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path_variables["VPR_ARCH_FILE"] = args.arch_file
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path_variables["OPENFPGA_ARCH_FILE"] = args.openfpga_arch_file
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path_variables["OPENFPGA_SIM_SETTING_FILE"] = args.openfpga_sim_setting_file
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path_variables["EXTERNAL_FABRIC_KEY_FILE"] = args.external_fabric_key_file
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path_variables["VPR_TESTBENCH_BLIF"] = args.top_module+".blif"
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path_variables["ACTIVITY_FILE"] = args.top_module+"_ace_out.act"
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path_variables["REFERENCE_VERILOG_TESTBENCH"] = args.top_module + \
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@ -357,6 +357,8 @@ def create_run_command(curr_job_dir, archfile, benchmark_obj, param, task_conf):
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task_gc.get("openfpga_arch_file")]
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command += ["--openfpga_sim_setting_file",
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task_gc.get("openfpga_sim_setting_file")]
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command += ["--external_fabric_key_file",
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task_gc.get("external_fabric_key_file")]
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if benchmark_obj.get("activity_file"):
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command += ["--activity_file", benchmark_obj.get("activity_file")]
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