diff --git a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem16K_40nm_bram.txt b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem16K_40nm_bram.txt
index 8cbf62755..327dbe9bf 100644
--- a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem16K_40nm_bram.txt
+++ b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem16K_40nm_bram.txt
@@ -1,6 +1,6 @@
 bram $__MY_DPRAM_2048x8
   init 0
-  abits 12
+  abits 11
   dbits 8
   groups 2
   ports  1  1
diff --git a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem16K_40nm_bram_map.v b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem16K_40nm_bram_map.v
index cc4881d77..35ec892dc 100644
--- a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem16K_40nm_bram_map.v
+++ b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem16K_40nm_bram_map.v
@@ -1,8 +1,8 @@
 module $__MY_DPRAM_2048x8 (
   output [0:7] B1DATA,
   input CLK1,
-  input [0:11] B1ADDR,
-  input [0:11] A1ADDR,
+  input [0:10] B1ADDR,
+  input [0:10] A1ADDR,
   input [0:7] A1DATA,
   input A1EN,
   input B1EN );
diff --git a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem16K_40nm_cell_sim.v b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem16K_40nm_cell_sim.v
index 5e772bf8d..9fc6a1aa1 100644
--- a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem16K_40nm_cell_sim.v
+++ b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem16K_40nm_cell_sim.v
@@ -5,11 +5,11 @@
 module dpram_2048x8_core (
   input wclk,
   input wen,
-  input [0:11] waddr,
+  input [0:10] waddr,
   input [0:7] data_in,
   input rclk,
   input ren,
-  input [0:11] raddr,
+  input [0:10] raddr,
   output [0:7] data_out );
 
   reg [0:7] ram[0:2047];
@@ -40,8 +40,8 @@ module dpram_2048x8 (
   input clk,
   input wen,
   input ren,
-  input [0:11] waddr,
-  input [0:11] raddr,
+  input [0:10] waddr,
+  input [0:10] raddr,
   input [0:7] data_in,
   output [0:7] data_out );