Update figures to be more accurate and clean
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@ -72,7 +72,6 @@ The file will look like this when finished:
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.. code-block:: python
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:linenos:
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:emphasize-lines: 44
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# Configuration file for running experiments
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@ -117,7 +116,7 @@ The file will look like this when finished:
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[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
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end_flow_with_test=
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#vpr_fpga_verilog_formal_verification_top_netlist=
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#LINE44 vpr_fpga_verilog_formal_verification_top_netlist=
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Our OpenFPGA task will now run the full testbench. We run the task with the following command from the root directory of OpenFPGA:
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@ -216,7 +215,7 @@ Using :ref:`fig_gpout_ports` as a guide, we can relate our task like :numref:`fi
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.. figure:: ./figures/lut6_Example_Spypad.svg
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:scale: 100%
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Diagram for ``frac_lut6_spypad``
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An illustrative example of the ``lut6`` spypad sourced from inside a logic element.
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We can view testbench waveforms with GTKWave by running the following command from the root directory:
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@ -232,9 +231,9 @@ The waveforms will appear similar to :numref:`fig_spypad_waves`
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.. _fig_spypad_waves:
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.. figure:: ./figures/spypad_waveforms.png
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:scale: 100%
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:width: 75%
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Spypad Waveforms
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Waveforms of ``frac_lut6`` Spypads
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Building Spypads
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~~~~~~~~~~~~~~~~
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@ -310,7 +309,7 @@ The architecture will now look like :numref:`fig_addf_example`
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.. figure:: ./figures/ADDF_Example_Spypad.svg
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:scale: 100%
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Diagram for ``ADDF``
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An illustrative example of the sumout spypad sourced from an adder inside a logic element. There are 10 logic elements in a CLB, and we are looking at the 1st logic element.
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We can view the waveform by running GTKWave:
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@ -325,7 +324,7 @@ The waveform should have some changes to its value. An example of what it may lo
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.. figure:: ./figures/spyadder_waveform.png
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:scale: 100%
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Sumout Waveform
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Waveforms of ``sumout`` Spypad
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Conclusion
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~~~~~~~~~~
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