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[Test] Disable ACE2 in implicit verilog test cases due to Yosys upgrade

This commit is contained in:
tangxifan 2021-10-30 14:49:56 -07:00
parent b7ad61227d
commit 40d11a45d9
3 changed files with 5 additions and 5 deletions
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2
openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga
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@ -10,7 +10,7 @@ read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
# Annotate the OpenFPGA architecture to VPR data base # Annotate the OpenFPGA architecture to VPR data base
# to debug use --verbose options # to debug use --verbose options
link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges link_openfpga_arch --sort_gsb_chan_node_in_edges
# Check and correct any naming conflicts in the BLIF netlist # Check and correct any naming conflicts in the BLIF netlist
check_netlist_naming_conflict --fix --report ./netlist_renaming.xml check_netlist_naming_conflict --fix --report ./netlist_renaming.xml

4
openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog/config/task.conf
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@ -9,7 +9,7 @@
[GENERAL] [GENERAL]
run_engine=openfpga_shell run_engine=openfpga_shell
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = true power_analysis = false
spice_output=false spice_output=false
verilog_output=true verilog_output=true
timeout_each_job = 20*60 timeout_each_job = 20*60
@ -18,7 +18,7 @@ fpga_flow=yosys_vpr
[OpenFPGA_SHELL] [OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
openfpga_verilog_default_net_type=none openfpga_verilog_default_net_type=none
[ARCHITECTURES] [ARCHITECTURES]

4
openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog_default_nettype_wire/config/task.conf
View File

@ -9,7 +9,7 @@
[GENERAL] [GENERAL]
run_engine=openfpga_shell run_engine=openfpga_shell
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = true power_analysis = false
spice_output=false spice_output=false
verilog_output=true verilog_output=true
timeout_each_job = 20*60 timeout_each_job = 20*60
@ -18,7 +18,7 @@ fpga_flow=yosys_vpr
[OpenFPGA_SHELL] [OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/implicit_verilog_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
openfpga_verilog_default_net_type=wire openfpga_verilog_default_net_type=wire
[ARCHITECTURES] [ARCHITECTURES]