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[Doc] Update naming convention for openfpga architecture files

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tangxifan 2022-03-20 10:22:41 +08:00
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openfpga_flow/openfpga_arch/README.md
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@ -31,6 +31,8 @@ Note that an OpenFPGA architecture can be applied to multiple VPR architecture f
- tree\_mux: If routing multiplexers are built with a tree-like structure - tree\_mux: If routing multiplexers are built with a tree-like structure
- <feature_size>: The technology node which the delay numbers are extracted from. - <feature_size>: The technology node which the delay numbers are extracted from.
- powergate : The FPGA has power-gating techniques applied. If not defined, there is no power-gating. - powergate : The FPGA has power-gating techniques applied. If not defined, there is no power-gating.
- GlobalTile<Int>Clk: How many clocks are defined through global ports from physical tiles. <Int> is the number of clocks - GlobalTile<Int>Clk<Port>: How many clocks are defined through global ports from physical tiles.
* <Int> is the number of clocks.
* <Port> means each clock pin belongs to a separated port. When not specified, all the clock pins are grouped in one port
Other features are used in naming should be listed here. Other features are used in naming should be listed here.