diff --git a/openfpga_flow/openfpga_arch/README.md b/openfpga_flow/openfpga_arch/README.md
index ed4a17815..6993554cc 100644
--- a/openfpga_flow/openfpga_arch/README.md
+++ b/openfpga_flow/openfpga_arch/README.md
@@ -31,6 +31,8 @@ Note that an OpenFPGA architecture can be applied to multiple VPR architecture f
 - tree\_mux: If routing multiplexers are built with a tree-like structure
 - <feature_size>: The technology node which the delay numbers are extracted from.
 - powergate : The FPGA has power-gating techniques applied. If not defined, there is no power-gating.
-- GlobalTile<Int>Clk: How many clocks are defined through global ports from physical tiles. <Int> is the number of clocks 
+- GlobalTile<Int>Clk<Port>: How many clocks are defined through global ports from physical tiles. 
+  * <Int> is the number of clocks.
+  * <Port> means each clock pin belongs to a separated port. When not specified, all the clock pins are grouped in one port
 
 Other features are used in naming should be listed here.