From 4064c29d495016db9367b91584abf0540a2cd283 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 4 Jul 2024 21:23:15 -0700
Subject: [PATCH] [test] updating arch for perimeter cb

---
 ...N4_tileable_IoSubtile_PerimeterCb_40nm.xml | 30 +++++++++----------
 1 file changed, 15 insertions(+), 15 deletions(-)

diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml
index ee4d3cf11..1af2645f1 100644
--- a/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml
@@ -65,10 +65,10 @@
         <output name="inpad" num_pins="1"/>
         <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
         <pinlocations pattern="custom">
-          <loc side="left">fpga_input[0:0].inpad</loc>
+          <loc side="left"></loc>
           <loc side="top"></loc>
-          <loc side="right">fpga_input[1:1].inpad</loc>
-          <loc side="bottom">fpga_input[2:3].inpad</loc>
+          <loc side="right"></loc>
+          <loc side="bottom">fpga_input[0:3].inpad</loc>
         </pinlocations>
       </sub_tile>
       <sub_tile name="fpga_output" capacity="2">
@@ -80,8 +80,8 @@
         <pinlocations pattern="custom">
           <loc side="left"></loc>
           <loc side="top"></loc>
-          <loc side="right">fpga_output[0:0].outpad</loc>
-          <loc side="bottom">fpga_output[1:1].outpad</loc>
+          <loc side="right"></loc>
+          <loc side="bottom">fpga_output[0:1].outpad</loc>
         </pinlocations>
       </sub_tile>
     </tile>
@@ -93,10 +93,10 @@
         <output name="inpad" num_pins="1"/>
         <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
         <pinlocations pattern="custom">
-          <loc side="left">fpga_input[0:0].inpad</loc>
+          <loc side="left">fpga_input[0:3].inpad</loc>
           <loc side="right"></loc>
-          <loc side="top">fpga_input[1:1].inpad</loc>
-          <loc side="bottom">fpga_input[2:3].inpad</loc>
+          <loc side="top"></loc>
+          <loc side="bottom"></loc>
         </pinlocations>
       </sub_tile>
       <sub_tile name="fpga_output" capacity="2">
@@ -106,10 +106,10 @@
         <input name="outpad" num_pins="1"/>
         <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
         <pinlocations pattern="custom">
-          <loc side="left"></loc>
+          <loc side="left">fpga_output[0:1].outpad</loc>
           <loc side="right"></loc>
-          <loc side="top">fpga_output[0:0].outpad</loc>
-          <loc side="bottom">fpga_output[1:1].outpad</loc>
+          <loc side="top"></loc>
+          <loc side="bottom"></loc>
         </pinlocations>
       </sub_tile>
     </tile>
@@ -150,8 +150,8 @@
         <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
         <pinlocations pattern="custom">
           <loc side="left"></loc>
-          <loc side="right">fpga_input[0:1].inpad</loc>
-          <loc side="top">fpga_input[2:3].inpad</loc>
+          <loc side="right">fpga_input[0:3].inpad</loc>
+          <loc side="top"></loc>
           <loc side="bottom"></loc>
         </pinlocations>
       </sub_tile>
@@ -163,8 +163,8 @@
         <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
         <pinlocations pattern="custom">
           <loc side="left"></loc>
-          <loc side="right">fpga_output[0:0].outpad</loc>
-          <loc side="top">fpga_output[1:1].outpad</loc>
+          <loc side="right">fpga_output[0:1].outpad</loc>
+          <loc side="top"></loc>
           <loc side="bottom"></loc>
         </pinlocations>
       </sub_tile>