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[core] format

This commit is contained in:
tangxifan 2023-01-06 17:50:47 -08:00
parent 12134f4106
commit 401b640852
6 changed files with 58 additions and 59 deletions
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3
openfpga/src/base/openfpga_spice_command.cpp
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@ -1,6 +1,7 @@
#include "openfpga_spice_command_template.h"
#include "openfpga_spice_command.h" #include "openfpga_spice_command.h"
#include "openfpga_spice_command_template.h"
/* begin namespace openfpga */ /* begin namespace openfpga */
namespace openfpga { namespace openfpga {

10
openfpga/src/base/openfpga_spice_command_template.h
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@ -24,8 +24,8 @@
* - TODO: generate_spice_sb_routing_testbench : generate SPICE testbenches for * - TODO: generate_spice_sb_routing_testbench : generate SPICE testbenches for
*routing circuit inside switch blocks *routing circuit inside switch blocks
*******************************************************************/ *******************************************************************/
#include "shell.h"
#include "openfpga_spice_template.h" #include "openfpga_spice_template.h"
#include "shell.h"
/* begin namespace openfpga */ /* begin namespace openfpga */
namespace openfpga { namespace openfpga {
@ -37,8 +37,7 @@ namespace openfpga {
*******************************************************************/ *******************************************************************/
template <class T> template <class T>
ShellCommandId add_write_fabric_spice_command_template( ShellCommandId add_write_fabric_spice_command_template(
openfpga::Shell<T>& shell, openfpga::Shell<T>& shell, const ShellCommandClassId& cmd_class_id,
const ShellCommandClassId& cmd_class_id,
const std::vector<ShellCommandId>& dependent_cmds) { const std::vector<ShellCommandId>& dependent_cmds) {
Command shell_cmd("write_fabric_spice"); Command shell_cmd("write_fabric_spice");
@ -59,7 +58,8 @@ ShellCommandId add_write_fabric_spice_command_template(
ShellCommandId shell_cmd_id = shell.add_command( ShellCommandId shell_cmd_id = shell.add_command(
shell_cmd, "generate SPICE netlists modeling full FPGA fabric"); shell_cmd, "generate SPICE netlists modeling full FPGA fabric");
shell.set_command_class(shell_cmd_id, cmd_class_id); shell.set_command_class(shell_cmd_id, cmd_class_id);
shell.set_command_execute_function(shell_cmd_id, write_fabric_spice_template<T>); shell.set_command_execute_function(shell_cmd_id,
write_fabric_spice_template<T>);
/* Add command dependency to the Shell */ /* Add command dependency to the Shell */
shell.set_command_dependency(shell_cmd_id, dependent_cmds); shell.set_command_dependency(shell_cmd_id, dependent_cmds);
@ -86,7 +86,7 @@ void add_spice_command_templates(openfpga::Shell<T>& shell) {
std::vector<ShellCommandId> fabric_spice_dependent_cmds; std::vector<ShellCommandId> fabric_spice_dependent_cmds;
fabric_spice_dependent_cmds.push_back(build_fabric_cmd_id); fabric_spice_dependent_cmds.push_back(build_fabric_cmd_id);
add_write_fabric_spice_command_template<T>(shell, openfpga_spice_cmd_class, add_write_fabric_spice_command_template<T>(shell, openfpga_spice_cmd_class,
fabric_spice_dependent_cmds); fabric_spice_dependent_cmds);
/******************************** /********************************
* TODO: Command 'write_spice_top_testbench' * TODO: Command 'write_spice_top_testbench'

8
openfpga/src/base/openfpga_spice_template.h
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@ -1,13 +1,13 @@
#ifndef OPENFPGA_SPICE_TEMPLATE_H #ifndef OPENFPGA_SPICE_TEMPLATE_H
#define OPENFPGA_SPICE_TEMPLATE_H #define OPENFPGA_SPICE_TEMPLATE_H
#include "vtr_log.h"
#include "vtr_time.h"
#include "command_exit_codes.h"
#include "spice_api.h"
#include "command.h" #include "command.h"
#include "command_context.h" #include "command_context.h"
#include "command_exit_codes.h"
#include "globals.h" #include "globals.h"
#include "spice_api.h"
#include "vtr_log.h"
#include "vtr_time.h"
/* begin namespace openfpga */ /* begin namespace openfpga */
namespace openfpga { namespace openfpga {

3
openfpga/src/base/openfpga_verilog_command.cpp
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@ -5,9 +5,10 @@
* - generate_fabric_verilog : generate Verilog netlists about FPGA fabric * - generate_fabric_verilog : generate Verilog netlists about FPGA fabric
* - generate_fabric_verilog_testbench : TODO: generate Verilog testbenches * - generate_fabric_verilog_testbench : TODO: generate Verilog testbenches
*******************************************************************/ *******************************************************************/
#include "openfpga_verilog_command_template.h"
#include "openfpga_verilog_command.h" #include "openfpga_verilog_command.h"
#include "openfpga_verilog_command_template.h"
/* begin namespace openfpga */ /* begin namespace openfpga */
namespace openfpga { namespace openfpga {

48
openfpga/src/base/openfpga_verilog_command_template.h
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@ -18,10 +18,9 @@ namespace openfpga {
* - Add associated options * - Add associated options
* - Add command dependency * - Add command dependency
*******************************************************************/ *******************************************************************/
template<class T> template <class T>
ShellCommandId add_write_fabric_verilog_command_template( ShellCommandId add_write_fabric_verilog_command_template(
openfpga::Shell<T>& shell, openfpga::Shell<T>& shell, const ShellCommandClassId& cmd_class_id,
const ShellCommandClassId& cmd_class_id,
const std::vector<ShellCommandId>& dependent_cmds) { const std::vector<ShellCommandId>& dependent_cmds) {
Command shell_cmd("write_fabric_verilog"); Command shell_cmd("write_fabric_verilog");
@ -67,7 +66,8 @@ ShellCommandId add_write_fabric_verilog_command_template(
ShellCommandId shell_cmd_id = shell.add_command( ShellCommandId shell_cmd_id = shell.add_command(
shell_cmd, "generate Verilog netlists modeling full FPGA fabric"); shell_cmd, "generate Verilog netlists modeling full FPGA fabric");
shell.set_command_class(shell_cmd_id, cmd_class_id); shell.set_command_class(shell_cmd_id, cmd_class_id);
shell.set_command_execute_function(shell_cmd_id, write_fabric_verilog_template<T>); shell.set_command_execute_function(shell_cmd_id,
write_fabric_verilog_template<T>);
/* Add command dependency to the Shell */ /* Add command dependency to the Shell */
shell.set_command_dependency(shell_cmd_id, dependent_cmds); shell.set_command_dependency(shell_cmd_id, dependent_cmds);
@ -80,10 +80,9 @@ ShellCommandId add_write_fabric_verilog_command_template(
* - add associated options * - add associated options
* - add command dependency * - add command dependency
*******************************************************************/ *******************************************************************/
template<class T> template <class T>
ShellCommandId add_write_full_testbench_command_template( ShellCommandId add_write_full_testbench_command_template(
openfpga::Shell<T>& shell, openfpga::Shell<T>& shell, const ShellCommandClassId& cmd_class_id,
const ShellCommandClassId& cmd_class_id,
const std::vector<ShellCommandId>& dependent_cmds) { const std::vector<ShellCommandId>& dependent_cmds) {
Command shell_cmd("write_full_testbench"); Command shell_cmd("write_full_testbench");
@ -165,7 +164,8 @@ ShellCommandId add_write_full_testbench_command_template(
ShellCommandId shell_cmd_id = shell.add_command( ShellCommandId shell_cmd_id = shell.add_command(
shell_cmd, "generate full testbenches for an fpga fabric"); shell_cmd, "generate full testbenches for an fpga fabric");
shell.set_command_class(shell_cmd_id, cmd_class_id); shell.set_command_class(shell_cmd_id, cmd_class_id);
shell.set_command_execute_function(shell_cmd_id, write_full_testbench_template<T>); shell.set_command_execute_function(shell_cmd_id,
write_full_testbench_template<T>);
/* add command dependency to the shell */ /* add command dependency to the shell */
shell.set_command_dependency(shell_cmd_id, dependent_cmds); shell.set_command_dependency(shell_cmd_id, dependent_cmds);
@ -178,10 +178,9 @@ ShellCommandId add_write_full_testbench_command_template(
* - add associated options * - add associated options
* - add command dependency * - add command dependency
*******************************************************************/ *******************************************************************/
template<class T> template <class T>
ShellCommandId add_write_preconfigured_fabric_wrapper_command_template( ShellCommandId add_write_preconfigured_fabric_wrapper_command_template(
openfpga::Shell<T>& shell, openfpga::Shell<T>& shell, const ShellCommandClassId& cmd_class_id,
const ShellCommandClassId& cmd_class_id,
const std::vector<ShellCommandId>& dependent_cmds) { const std::vector<ShellCommandId>& dependent_cmds) {
Command shell_cmd("write_preconfigured_fabric_wrapper"); Command shell_cmd("write_preconfigured_fabric_wrapper");
@ -243,8 +242,8 @@ ShellCommandId add_write_preconfigured_fabric_wrapper_command_template(
ShellCommandId shell_cmd_id = shell.add_command( ShellCommandId shell_cmd_id = shell.add_command(
shell_cmd, "generate a wrapper for a pre-configured fpga fabric"); shell_cmd, "generate a wrapper for a pre-configured fpga fabric");
shell.set_command_class(shell_cmd_id, cmd_class_id); shell.set_command_class(shell_cmd_id, cmd_class_id);
shell.set_command_execute_function(shell_cmd_id, shell.set_command_execute_function(
write_preconfigured_fabric_wrapper_template<T>); shell_cmd_id, write_preconfigured_fabric_wrapper_template<T>);
/* add command dependency to the shell */ /* add command dependency to the shell */
shell.set_command_dependency(shell_cmd_id, dependent_cmds); shell.set_command_dependency(shell_cmd_id, dependent_cmds);
@ -257,10 +256,9 @@ ShellCommandId add_write_preconfigured_fabric_wrapper_command_template(
* - Add associated options * - Add associated options
* - Add command dependency * - Add command dependency
*******************************************************************/ *******************************************************************/
template<class T> template <class T>
ShellCommandId add_write_preconfigured_testbench_command_template( ShellCommandId add_write_preconfigured_testbench_command_template(
openfpga::Shell<T>& shell, openfpga::Shell<T>& shell, const ShellCommandClassId& cmd_class_id,
const ShellCommandClassId& cmd_class_id,
const std::vector<ShellCommandId>& dependent_cmds) { const std::vector<ShellCommandId>& dependent_cmds) {
Command shell_cmd("write_preconfigured_testbench"); Command shell_cmd("write_preconfigured_testbench");
@ -337,10 +335,9 @@ ShellCommandId add_write_preconfigured_testbench_command_template(
* - Add associated options * - Add associated options
* - Add command dependency * - Add command dependency
*******************************************************************/ *******************************************************************/
template<class T> template <class T>
ShellCommandId add_write_simulation_task_info_command_template( ShellCommandId add_write_simulation_task_info_command_template(
openfpga::Shell<T>& shell, openfpga::Shell<T>& shell, const ShellCommandClassId& cmd_class_id,
const ShellCommandClassId& cmd_class_id,
const std::vector<ShellCommandId>& dependent_cmds) { const std::vector<ShellCommandId>& dependent_cmds) {
Command shell_cmd("write_simulation_task_info"); Command shell_cmd("write_simulation_task_info");
@ -385,7 +382,8 @@ ShellCommandId add_write_simulation_task_info_command_template(
ShellCommandId shell_cmd_id = shell.add_command( ShellCommandId shell_cmd_id = shell.add_command(
shell_cmd, "generate an interchangable simulation task configuration file"); shell_cmd, "generate an interchangable simulation task configuration file");
shell.set_command_class(shell_cmd_id, cmd_class_id); shell.set_command_class(shell_cmd_id, cmd_class_id);
shell.set_command_execute_function(shell_cmd_id, write_simulation_task_info_template<T>); shell.set_command_execute_function(shell_cmd_id,
write_simulation_task_info_template<T>);
/* Add command dependency to the Shell */ /* Add command dependency to the Shell */
shell.set_command_dependency(shell_cmd_id, dependent_cmds); shell.set_command_dependency(shell_cmd_id, dependent_cmds);
@ -393,7 +391,7 @@ ShellCommandId add_write_simulation_task_info_command_template(
return shell_cmd_id; return shell_cmd_id;
} }
template<class T> template <class T>
void add_verilog_command_templates(openfpga::Shell<T>& shell) { void add_verilog_command_templates(openfpga::Shell<T>& shell) {
/* Get the unique id of 'build_fabric' command which is to be used in creating /* Get the unique id of 'build_fabric' command which is to be used in creating
* the dependency graph */ * the dependency graph */
@ -411,8 +409,8 @@ void add_verilog_command_templates(openfpga::Shell<T>& shell) {
* 'build_fabric' */ * 'build_fabric' */
std::vector<ShellCommandId> fabric_verilog_dependent_cmds; std::vector<ShellCommandId> fabric_verilog_dependent_cmds;
fabric_verilog_dependent_cmds.push_back(build_fabric_cmd_id); fabric_verilog_dependent_cmds.push_back(build_fabric_cmd_id);
add_write_fabric_verilog_command_template<T>(shell, openfpga_verilog_cmd_class, add_write_fabric_verilog_command_template<T>(
fabric_verilog_dependent_cmds); shell, openfpga_verilog_cmd_class, fabric_verilog_dependent_cmds);
/******************************** /********************************
* Command 'write_full_testbench' * Command 'write_full_testbench'
@ -421,8 +419,8 @@ void add_verilog_command_templates(openfpga::Shell<T>& shell) {
* 'build_fabric' */ * 'build_fabric' */
std::vector<ShellCommandId> full_testbench_dependent_cmds; std::vector<ShellCommandId> full_testbench_dependent_cmds;
full_testbench_dependent_cmds.push_back(build_fabric_cmd_id); full_testbench_dependent_cmds.push_back(build_fabric_cmd_id);
add_write_full_testbench_command_template<T>(shell, openfpga_verilog_cmd_class, add_write_full_testbench_command_template<T>(
full_testbench_dependent_cmds); shell, openfpga_verilog_cmd_class, full_testbench_dependent_cmds);
/******************************** /********************************
* Command 'write_preconfigured_fabric_wrapper' * Command 'write_preconfigured_fabric_wrapper'

45
openfpga/src/base/openfpga_verilog_template.h
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@ -4,16 +4,16 @@
/******************************************************************** /********************************************************************
* This file includes functions to compress the hierachy of routing architecture * This file includes functions to compress the hierachy of routing architecture
*******************************************************************/ *******************************************************************/
#include "vtr_log.h"
#include "vtr_time.h"
#include "command_exit_codes.h"
#include "openfpga_scale.h"
#include "command.h" #include "command.h"
#include "command_context.h" #include "command_context.h"
#include "verilog_api.h" #include "command_exit_codes.h"
#include "read_xml_pin_constraints.h"
#include "read_xml_bus_group.h"
#include "globals.h" #include "globals.h"
#include "openfpga_scale.h"
#include "read_xml_bus_group.h"
#include "read_xml_pin_constraints.h"
#include "verilog_api.h"
#include "vtr_log.h"
#include "vtr_time.h"
/* begin namespace openfpga */ /* begin namespace openfpga */
namespace openfpga { namespace openfpga {
@ -21,9 +21,9 @@ namespace openfpga {
/******************************************************************** /********************************************************************
* A wrapper function to call the fabric Verilog generator of FPGA-Verilog * A wrapper function to call the fabric Verilog generator of FPGA-Verilog
*******************************************************************/ *******************************************************************/
template<class T> template <class T>
int write_fabric_verilog_template(T& openfpga_ctx, const Command& cmd, int write_fabric_verilog_template(T& openfpga_ctx, const Command& cmd,
const CommandContext& cmd_context) { const CommandContext& cmd_context) {
CommandOptionId opt_output_dir = cmd.option("file"); CommandOptionId opt_output_dir = cmd.option("file");
CommandOptionId opt_explicit_port_mapping = CommandOptionId opt_explicit_port_mapping =
cmd.option("explicit_port_mapping"); cmd.option("explicit_port_mapping");
@ -71,10 +71,9 @@ int write_fabric_verilog_template(T& openfpga_ctx, const Command& cmd,
/******************************************************************** /********************************************************************
* A wrapper function to call the full testbench generator of FPGA-Verilog * A wrapper function to call the full testbench generator of FPGA-Verilog
*******************************************************************/ *******************************************************************/
template<class T> template <class T>
int write_full_testbench_template(const T& openfpga_ctx, int write_full_testbench_template(const T& openfpga_ctx, const Command& cmd,
const Command& cmd, const CommandContext& cmd_context) {
const CommandContext& cmd_context) {
CommandOptionId opt_output_dir = cmd.option("file"); CommandOptionId opt_output_dir = cmd.option("file");
CommandOptionId opt_bitstream = cmd.option("bitstream"); CommandOptionId opt_bitstream = cmd.option("bitstream");
CommandOptionId opt_fabric_netlist = cmd.option("fabric_netlist_file_path"); CommandOptionId opt_fabric_netlist = cmd.option("fabric_netlist_file_path");
@ -145,10 +144,10 @@ int write_full_testbench_template(const T& openfpga_ctx,
* A wrapper function to call the preconfigured wrapper generator of * A wrapper function to call the preconfigured wrapper generator of
*FPGA-Verilog *FPGA-Verilog
*******************************************************************/ *******************************************************************/
template<class T> template <class T>
int write_preconfigured_fabric_wrapper_template(const T& openfpga_ctx, int write_preconfigured_fabric_wrapper_template(
const Command& cmd, const T& openfpga_ctx, const Command& cmd,
const CommandContext& cmd_context) { const CommandContext& cmd_context) {
CommandOptionId opt_output_dir = cmd.option("file"); CommandOptionId opt_output_dir = cmd.option("file");
CommandOptionId opt_fabric_netlist = cmd.option("fabric_netlist_file_path"); CommandOptionId opt_fabric_netlist = cmd.option("fabric_netlist_file_path");
CommandOptionId opt_pcf = cmd.option("pin_constraints_file"); CommandOptionId opt_pcf = cmd.option("pin_constraints_file");
@ -212,10 +211,10 @@ int write_preconfigured_fabric_wrapper_template(const T& openfpga_ctx,
* A wrapper function to call the preconfigured testbench generator of * A wrapper function to call the preconfigured testbench generator of
*FPGA-Verilog *FPGA-Verilog
*******************************************************************/ *******************************************************************/
template<class T> template <class T>
int write_preconfigured_testbench_template(const T& openfpga_ctx, int write_preconfigured_testbench_template(const T& openfpga_ctx,
const Command& cmd, const Command& cmd,
const CommandContext& cmd_context) { const CommandContext& cmd_context) {
CommandOptionId opt_output_dir = cmd.option("file"); CommandOptionId opt_output_dir = cmd.option("file");
CommandOptionId opt_pcf = cmd.option("pin_constraints_file"); CommandOptionId opt_pcf = cmd.option("pin_constraints_file");
CommandOptionId opt_bgf = cmd.option("bus_group_file"); CommandOptionId opt_bgf = cmd.option("bus_group_file");
@ -275,10 +274,10 @@ int write_preconfigured_testbench_template(const T& openfpga_ctx,
* A wrapper function to call the simulation task information generator of * A wrapper function to call the simulation task information generator of
*FPGA-Verilog *FPGA-Verilog
*******************************************************************/ *******************************************************************/
template<class T> template <class T>
int write_simulation_task_info_template(const T& openfpga_ctx, int write_simulation_task_info_template(const T& openfpga_ctx,
const Command& cmd, const Command& cmd,
const CommandContext& cmd_context) { const CommandContext& cmd_context) {
CommandOptionId opt_file = cmd.option("file"); CommandOptionId opt_file = cmd.option("file");
CommandOptionId opt_hdl_dir = cmd.option("hdl_dir"); CommandOptionId opt_hdl_dir = cmd.option("hdl_dir");
CommandOptionId opt_reference_benchmark = CommandOptionId opt_reference_benchmark =