[Tool] Bug fix for combinational benchmarks in pre-config testbench generation
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@ -143,8 +143,9 @@ int print_verilog_preconfig_top_module_connect_global_ports(std::fstream &fp,
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}
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}
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/* If constrained to an open net, we assign it to a default value */
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if (std::string(PIN_CONSTRAINT_OPEN_NET) == constrained_net_name) {
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/* If constrained to an open net or there is no clock in the benchmark, we assign it to a default value */
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if ( (std::string(PIN_CONSTRAINT_OPEN_NET) == constrained_net_name)
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|| (true == benchmark_clock_port_names.empty())) {
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std::vector<size_t> default_values(1, fabric_global_ports.global_port_default_value(global_port_id));
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print_verilog_wire_constant_values(fp, module_clock_pin, default_values);
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continue;
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