From 3f6ac4186861647cb2fcd7eed2ab23b0b9498255 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 20 Sep 2021 11:21:58 -0700 Subject: [PATCH] [Test] Deploy the WLR test to the basic regression tests --- openfpga_flow/regression_test_scripts/basic_reg_test.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index 5bef6a05f..531ba5f42 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -55,6 +55,7 @@ run-task basic_tests/preconfig_testbench/memory_bank --debug --show_thread_logs echo -e "Testing physical design friendly memory bank configuration protocol of a K4N4 FPGA"; run-task basic_tests/full_testbench/ql_memory_bank --debug --show_thread_logs +run-task basic_tests/full_testbench/ql_memory_bank_use_wlr --debug --show_thread_logs echo -e "Testing testbenches without self checking features"; run-task basic_tests/full_testbench/full_testbench_without_self_checking --debug --show_thread_logs