From 3f08b83b3a9b1fd692b08c6a1986f76b1ec7d0e0 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 21 Jun 2024 17:12:10 -0700 Subject: [PATCH] [core] remove restrictions on 1 clock tree definition --- .../src/annotation/append_clock_rr_graph.cpp | 16 ++++------------ 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/openfpga/src/annotation/append_clock_rr_graph.cpp b/openfpga/src/annotation/append_clock_rr_graph.cpp index dee65e605..ac48b5cef 100644 --- a/openfpga/src/annotation/append_clock_rr_graph.cpp +++ b/openfpga/src/annotation/append_clock_rr_graph.cpp @@ -525,8 +525,8 @@ static void add_rr_graph_block_clock_edges( chan_coord, itree, ilvl, ClockTreePinId(ipin), node_dir)) { /* Create edges */ VTR_ASSERT(rr_graph_view.valid_node(des_node)); - rr_graph_builder.create_edge( - src_node, des_node, clk_ntwk.default_driver_switch(), false); + rr_graph_builder.create_edge(src_node, des_node, + clk_ntwk.default_driver_switch(), false); edge_count++; } VTR_LOGV(verbose, "\tWill add %lu edges to other clock nodes\n", @@ -541,8 +541,8 @@ static void add_rr_graph_block_clock_edges( itree, ClockTreePinId(ipin))) { /* Create edges */ VTR_ASSERT(rr_graph_view.valid_node(des_node)); - rr_graph_builder.create_edge( - src_node, des_node, clk_ntwk.default_tap_switch(), false); + rr_graph_builder.create_edge(src_node, des_node, + clk_ntwk.default_tap_switch(), false); edge_count++; } VTR_LOGV(verbose, "\tWill add %lu edges to other IPIN\n", @@ -638,14 +638,6 @@ int append_clock_rr_graph(DeviceContext& vpr_device_ctx, return CMD_EXEC_SUCCESS; } - /* Report any clock structure we do not support yet! */ - if (clk_ntwk.num_trees() > 1) { - VTR_LOG( - "Currently only support 1 clock tree in programmable clock " - "architecture\nPlease update your clock architecture definition\n"); - return CMD_EXEC_FATAL_ERROR; - } - /* Estimate the number of nodes and pre-allocate */ size_t orig_num_nodes = vpr_device_ctx.rr_graph.num_nodes(); size_t num_clock_nodes = estimate_clock_rr_graph_num_nodes(