tutorial additions

This commit is contained in:
Steve Corey 2018-07-03 15:04:09 -06:00
parent 2cc4027ab0
commit 3f00ce365e
2 changed files with 69 additions and 17 deletions

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"arch = \"~/OpenFPGA/tangxifan-eda-tools/branches/vpr7_rram/libarchfpga/arch/sample_arch.xml\"\n",
"circuit = \"~/OpenFPGA/tangxifan-eda-tools/trunk/MPACK1.5_FLOW/BENCHMARKS/test_case1/add16_new.blif\""
"arch = \"./tutorial/example_arch.xml\"\n",
"circuit = \"./tutorial/example_circuit.blif\""
]
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"source": [
"When you ran the tool, a number of text output files are created that report on what the tool did. Open the file \"OpenFPGA/tutorial/example_circuit.place\" in a text editor and note on line 2: \"Array size: 2 x 2 logic blocks\". This is a report that when the tool placed and routed the logic, it ended up in a 2 x 2 grid."
]
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"Now open the file \"OpenFPGA/tutorial/example_arch.xml\" in a text editor. Go to line 51 and change:\n",
"\n",
"<pb_type name=\"io\" capacity=\"1\">\n",
"\n",
"to:\n",
"\n",
"<pb_type name=\"io\" capacity=\"3\">\n",
"\n",
"Now, instead of each input/output block only having 1 input or output, they can have 3 inputs or outputs.\n",
"\n",
"Run the tool again:"
]
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"source": [
"os.system(command_line_nodisp)"
]
},
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"source": [
"Re-open the file \"OpenFPGA/tutorial/example_circuit.place\" in a text editor and note that the logic is now placed in one block.\n",
"\n",
"The simple change to the number of inputs or outputs per I/O block let the placement and routing tool use less space on the FPGA for the circuit."
]
}
],
"metadata": {

4
tutorial/.gitignore vendored Normal file
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*.out
*.place
*.route
*.net