riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Add disclaimer in architecture file

This commit is contained in:
Aur??Lien ALACCHI 2021-01-29 09:22:23 -07:00
parent f50d033037
commit 3ef0047f3e
1 changed files with 2 additions and 23 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

25
openfpga_flow/vpr_arch/k4_frac_N4_tileable_lutram_40nm.xml
View File

@ -4,7 +4,8 @@
- 40 nm technology
- General purpose logic block:
K = 4, N = 4, fracturable 4 LUTs (can operate as one 4-LUT or two 3-LUTs with all 3 inputs shared)
with optionally registered outputs
with optionally registered outputs with 4x1 bits SPRAM for dispersed memory functions.
- This architecture ONLY MIMICS LUT-RAM FUNCTIONALITY
- Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
Details on Modelling:
@ -24,28 +25,6 @@
that describe them.
-->
<models>
<!--model name="adder">
<input_ports>
<port name="a" combinational_sink_ports="sumout cout"/>
<port name="b" combinational_sink_ports="sumout cout"/>
<port name="cin" combinational_sink_ports="sumout cout"/>
</input_ports>
<output_ports>
<port name="cout"/>
<port name="sumout"/>
</output_ports>
</model-->
<!--model name="mux4">
<input_ports>
<port name="frac0_out" combinational_sink_ports="mux4_out"/>
<port name="frac1_out" combinational_sink_ports="mux4_out"/>
<port name="frac2_out" combinational_sink_ports="mux4_out"/>
<port name="frac3_out" combinational_sink_ports="mux4_out"/>
</input_ports>
<output_ports>
<port name="mux4_out"/>
</output_ports>
</model-->
<!-- A virtual model for I/O to be used in the physical mode of io block -->
<model name="io">
<input_ports>