Add the reference_file to the index.rst
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@ -45,3 +45,5 @@ OpenFPGA widely uses XML format for interchangeable files
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fabric_pin_physical_location_file
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fabric_pin_physical_location_file
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fabric_hierarchy_file
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fabric_hierarchy_file
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reference_file
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@ -33,8 +33,6 @@ int report_reference(const char* fname, const std::string& module_name,
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ModuleId parent_module = module_manager.find_module(module_name);
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ModuleId parent_module = module_manager.find_module(module_name);
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if (false == module_manager.valid_module_id(parent_module)) {
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if (false == module_manager.valid_module_id(parent_module)) {
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VTR_LOG_ERROR("Module %s doesn't exist\n", module_name.c_str());
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VTR_LOG_ERROR("Module %s doesn't exist\n", module_name.c_str());
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if (verbose) write_module_to_file(fname, module_manager);
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return CMD_EXEC_FATAL_ERROR;
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return CMD_EXEC_FATAL_ERROR;
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}
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}
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@ -122,42 +120,4 @@ int write_reference_to_file(const char* fname, const ModuleId& parent_module,
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return CMD_EXEC_SUCCESS;
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return CMD_EXEC_SUCCESS;
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}
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}
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/********************************************************************
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* write all modules to a given file
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*******************************************************************/
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void write_module_to_file(const char* fname,
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const ModuleManager& module_manager) {
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std::fstream fp;
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fp.open(std::string(fname), std::fstream::out | std::fstream::trunc);
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openfpga::check_file_stream(fname, fp);
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fp << "module_count: " << module_manager.modules().size() << std::endl;
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for (ModuleId curr_module : module_manager.modules()) {
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std::string curr_module_name = module_manager.module_name(curr_module);
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fp << "module: " << curr_module_name.c_str() << std::endl;
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for (ModuleId child_module : module_manager.child_modules(curr_module)) {
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std::string child_module_name = module_manager.module_name(child_module);
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std::vector<size_t> child_inst_vec =
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module_manager.child_module_instances(curr_module, child_module);
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fp << " - child_module:" << child_module_name.c_str() << std::endl
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<< " instance_count:" << child_inst_vec.size() << std::endl
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<< " instances:" << std::endl;
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for (size_t inst_id : child_inst_vec) {
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std::string inst_name =
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module_manager.instance_name(curr_module, child_module, inst_id);
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fp << " - ";
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if (true == inst_name.empty()) {
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fp << generate_instance_name(child_module_name, inst_id) << std::endl;
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} else {
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fp << inst_name << std::endl;
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}
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}
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}
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}
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fp.close();
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}
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} /* end namespace openfpga */
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} /* end namespace openfpga */
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@ -25,9 +25,6 @@ int write_reference_to_file(const char* fname, const ModuleId& parent_module,
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const ModuleManager& module_manager,
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const ModuleManager& module_manager,
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const bool& include_time_stamp,
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const bool& include_time_stamp,
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const bool& verbose);
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const bool& verbose);
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void write_module_to_file(const char* fname,
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const ModuleManager& module_manager);
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} /* end namespace openfpga */
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} /* end namespace openfpga */
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#endif
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#endif
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