From 3e5ebc3dc3717eb98282e414792c54cba1898079 Mon Sep 17 00:00:00 2001
From: Lalit Sharma <lsharma@quicklogic.com>
Date: Mon, 19 Apr 2021 05:55:10 -0700
Subject: [PATCH] Updating qlf_yosys.tcl file with correct condition to pick
 .so

---
 openfpga_flow/misc/qlf_yosys.tcl | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/openfpga_flow/misc/qlf_yosys.tcl b/openfpga_flow/misc/qlf_yosys.tcl
index 9d0065826..b0c362ffc 100644
--- a/openfpga_flow/misc/qlf_yosys.tcl
+++ b/openfpga_flow/misc/qlf_yosys.tcl
@@ -1,8 +1,10 @@
 # Yosys synthesis script for ${TOP_MODULE}
 yosys -import
-
-if { [info procs ql-qlf] == {} } { plugin -i ql-qlf }
-yosys -import  ;# ingest plugin commands
+if { [info exists ::env(YOSYS)] } {
+    set yosys_dir [file dirname $env(YOSYS)]
+    if { [file exists $yosys_dir/../share/yosys/plugins/ql-qlf.so] == 1 } { plugin -i ql-qlf }
+    yosys -import  ;# ingest plugin commands
+} 
 
 # Read verilog files
 ${READ_VERILOG_FILE}