riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[FPGA-Verilog] Add big/little endian support when instanciate reference benchmarks

This commit is contained in:
tangxifan 2022-02-19 09:15:38 -08:00
parent 7645d5332d
commit 3e43a60fdc
1 changed files with 6 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
View File

@ -156,8 +156,12 @@ void print_verilog_testbench_benchmark_instance(std::fstream& fp,
if (bus_id) { if (bus_id) {
fp << "{"; fp << "{";
int pin_counter = 0; int pin_counter = 0;
/* Include all the pins */ /* Include all the pins: If it follows little endian, reverse the pin sequence */
for (const BusPinId& pin : bus_group.bus_pins(bus_id)) { std::vector<BusPinId> bus_pins = bus_group.bus_pins(bus_id);
if (!bus_group.is_big_endian(bus_id)) {
std::reverse(bus_pins.begin(), bus_pins.end());
}
for (const BusPinId& pin : bus_pins) {
if (0 < pin_counter) { if (0 < pin_counter) {
fp << ", "; fp << ", ";
} }