From 3d8200e2175d1792809ef6753de15113c534e360 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 26 Jun 2019 15:51:11 -0600 Subject: [PATCH] critical bug fixed in bitstream generator for compact routing hierarchy --- vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp | 55 +++++++++++-------- .../bitstream/fpga_bitstream_routing.c | 19 +++---- .../fpga_x2p/verilog/verilog_report_timing.c | 5 -- .../SRC/fpga_x2p/verilog/verilog_routing.c | 7 +-- 4 files changed, 41 insertions(+), 45 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp index 766d7e00f..f0d59fd9b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp @@ -2124,32 +2124,41 @@ bool RRGSB::is_sb_node_mirror(const RRGSB& cand, if (is_short_conkt != cand.is_sb_node_passing_wire(node_side, track_id)) { return false; - } else { /* check driving rr_nodes */ - if ( node->num_drive_rr_nodes != cand_node->num_drive_rr_nodes ) { + } + + if (true == is_short_conkt) { + /* Since, both are pass wires, + * The two node should be equivalent + * we can return here + */ + return true; + } + + /* For non-passing wires, check driving rr_nodes */ + if ( node->num_drive_rr_nodes != cand_node->num_drive_rr_nodes ) { + return false; + } + for (size_t inode = 0; inode < size_t(node->num_drive_rr_nodes); ++inode) { + /* node type should be the same */ + if ( node->drive_rr_nodes[inode]->type + != cand_node->drive_rr_nodes[inode]->type) { return false; } - for (size_t inode = 0; inode < size_t(node->num_drive_rr_nodes); ++inode) { - /* node type should be the same */ - if ( node->drive_rr_nodes[inode]->type - != cand_node->drive_rr_nodes[inode]->type) { - return false; - } - /* switch type should be the same */ - if ( node->drive_switches[inode] - != cand_node->drive_switches[inode]) { - return false; - } - int src_node_id, des_node_id; - enum e_side src_node_side, des_node_side; - this->get_node_side_and_index(node->drive_rr_nodes[inode], OUT_PORT, &src_node_side, &src_node_id); - cand.get_node_side_and_index(cand_node->drive_rr_nodes[inode], OUT_PORT, &des_node_side, &des_node_id); - if (src_node_id != des_node_id) { - return false; - } - if (src_node_side != des_node_side) { - return false; - } + /* switch type should be the same */ + if ( node->drive_switches[inode] + != cand_node->drive_switches[inode]) { + return false; } + int src_node_id, des_node_id; + enum e_side src_node_side, des_node_side; + this->get_node_side_and_index(node->drive_rr_nodes[inode], OUT_PORT, &src_node_side, &src_node_id); + cand.get_node_side_and_index(cand_node->drive_rr_nodes[inode], OUT_PORT, &des_node_side, &des_node_id); + if (src_node_id != des_node_id) { + return false; + } + if (src_node_side != des_node_side) { + return false; + } } return true; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream_routing.c index 866de67b7..968cf8859 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream_routing.c @@ -859,24 +859,21 @@ void fpga_spice_generate_bitstream_routing_resources(char* routing_bitstream_log /* Connection Boxes */ if (TRUE == compact_routing_hierarchy) { - vpr_printf(TIO_MESSAGE_INFO,"Generating bitstream for Connection blocks - X direction ...\n"); - /* X - channels [1...nx][0..ny]*/ - for (int iy = 0; iy < (ny + 1); ++iy) { - for (int ix = 1; ix < (nx + 1); ++ix) { + DeviceCoordinator gsb_range = device_rr_gsb.get_gsb_range(); + + vpr_printf(TIO_MESSAGE_INFO,"Generating bitstream for Connection blocks ...\n"); + + for (size_t ix = 0; ix < gsb_range.get_x(); ++ix) { + for (size_t iy = 0; iy < gsb_range.get_y(); ++iy) { const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy); + /* X - channels [1...nx][0..ny]*/ if ((TRUE == is_cb_exist(CHANX, ix, iy)) &&(true == rr_gsb.is_cb_exist(CHANX))) { fpga_spice_generate_bitstream_routing_connection_box_subckt(fp, rr_gsb, CHANX, cur_sram_orgz_info); } - } - } - /* Y - channels [1...ny][0..nx]*/ - vpr_printf(TIO_MESSAGE_INFO,"Generating bitstream for Connection blocks - Y direction ...\n"); - for (int ix = 0; ix < (nx + 1); ++ix) { - for (int iy = 1; iy < (ny + 1); ++iy) { - const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy); + /* Y - channels [1...ny][0..nx]*/ if ((TRUE == is_cb_exist(CHANY, ix, iy)) &&(true == rr_gsb.is_cb_exist(CHANY))) { fpga_spice_generate_bitstream_routing_connection_box_subckt(fp, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_report_timing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_report_timing.c index 7cba7f692..692698374 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_report_timing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_report_timing.c @@ -519,8 +519,6 @@ std::vector build_ending_rr_node_for_one_sb_wire(t_rr_node* wire_rr_ std::vector end_rr_nodes; end_rr_nodes.clear(); - /* Find where the destination pin belongs to */ - DeviceCoordinator wire_end_coordinator = get_track_rr_node_end_coordinator(wire_rr_node); /* Get the cooridinator of the destination SB */ DeviceCoordinator end_sb_coordinator = get_chan_node_ending_sb_coordinator(wire_rr_node); /* Get the sb */ @@ -1246,7 +1244,6 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, int path_cnt) { int L_wire; int ix, iy; - int cur_sb_x, cur_sb_y; int end_sb_x, end_sb_y; t_cb* next_cb = NULL; t_sb* next_sb = NULL; @@ -1394,8 +1391,6 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, } /* Get the base coordinate of src_sb */ - cur_sb_x = src_sb_info->x; - cur_sb_y = src_sb_info->y; /* 4 cases: */ if ((INC_DIRECTION == src_rr_node->direction) &&(CHANX == src_rr_node->type)) { diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index 3df663300..502b93163 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -3895,15 +3895,10 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, for (size_t iy = 0; iy < cb_range.get_y(); ++iy) { const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy); update_routing_connection_box_conf_bits(cur_sram_orgz_info, rr_gsb, CHANX); - } - } - - for (size_t ix = 0; ix < cb_range.get_x(); ++ix) { - for (size_t iy = 0; iy < cb_range.get_y(); ++iy) { - const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy); update_routing_connection_box_conf_bits(cur_sram_orgz_info, rr_gsb, CHANY); } } + /* Free */ free_sram_orgz_info(stamped_sram_orgz_info, stamped_sram_orgz_info->type); } else {