From 3d7adb3dd974a0a1a0c17a25f8b59e3bb66682f8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 9 Aug 2019 15:52:28 -0600 Subject: [PATCH] start developing parsers for delay values --- .../fpga_spice_include/circuit_library.cpp | 131 ++++++++++++++++-- .../SRC/fpga_spice_include/circuit_library.h | 11 +- 2 files changed, 125 insertions(+), 17 deletions(-) diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp index 132186cfe..dd7862c3c 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.cpp @@ -66,8 +66,7 @@ std::vector CircuitLibrary::input_ports(const CircuitModelId& cir std::vector input_ports; for (const auto& port_id : ports(circuit_model_id)) { /* We skip output ports */ - if ( (SPICE_MODEL_PORT_OUTPUT == port_type(circuit_model_id, port_id)) - || (SPICE_MODEL_PORT_INOUT == port_type(circuit_model_id, port_id)) ) { + if ( false == is_input_port(circuit_model_id, port_id) ) { continue; } input_ports.push_back(port_id); @@ -81,12 +80,11 @@ std::vector CircuitLibrary::input_ports(const CircuitModelId& cir std::vector CircuitLibrary::output_ports(const CircuitModelId& circuit_model_id) const { std::vector output_ports; for (const auto& port_id : ports(circuit_model_id)) { - /* We skip output ports */ - if ( (SPICE_MODEL_PORT_OUTPUT != port_type(circuit_model_id, port_id)) - && (SPICE_MODEL_PORT_INOUT != port_type(circuit_model_id, port_id)) ) { + /* We skip input ports */ + if ( false == is_output_port(circuit_model_id, port_id) ) { continue; } - output_ports.push_back(port_id); + output_ports.push_back(port_id); } return output_ports; } @@ -201,9 +199,47 @@ bool CircuitLibrary::is_lut_intermediate_buffered(const CircuitModelId& circuit_ /************************************************************************ * Public Accessors : Basic data query on Circuit Porst ***********************************************************************/ + +/* identify if this port is an input port */ +bool CircuitLibrary::is_input_port(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const { + /* validate the circuit_model_id and circuit_port_id */ + VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + /* Only SPICE_MODEL_OUTPUT AND INOUT are considered as outputs */ + return ( (SPICE_MODEL_PORT_OUTPUT != port_type(circuit_model_id, circuit_port_id)) + && (SPICE_MODEL_PORT_INOUT != port_type(circuit_model_id, circuit_port_id)) ); +} + +/* identify if this port is an output port */ +bool CircuitLibrary::is_output_port(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const { + /* validate the circuit_model_id and circuit_port_id */ + VTR_ASSERT_SAFE(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + /* Only SPICE_MODEL_OUTPUT AND INOUT are considered as outputs */ + return ( (SPICE_MODEL_PORT_OUTPUT == port_type(circuit_model_id, circuit_port_id)) + || (SPICE_MODEL_PORT_INOUT == port_type(circuit_model_id, circuit_port_id)) ); +} + +/* Given a name and return the port id */ +CircuitPortId CircuitLibrary::port(const CircuitModelId& circuit_model_id, const std::string& name) const { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + /* Walk through the ports and try to find a matched name */ + CircuitPortId ret = CIRCUIT_PORT_OPEN_ID; + size_t num_found = 0; + for (auto port_id : ports(circuit_model_id)) { + if (0 != name.compare(port_prefix(circuit_model_id, port_id))) { + continue; /* Not the one, go to the next*/ + } + ret = port_id; /* Find one */ + num_found++; + } + /* Make sure we will not find two ports with the same name */ + VTR_ASSERT_SAFE( (0 == num_found) || (1 == num_found) ); + return ret; +} + /* Access the type of a port of a circuit model */ size_t CircuitLibrary::num_ports(const CircuitModelId& circuit_model_id) const { - /* validate the circuit_port_id */ + /* validate the circuit_model_id */ VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); return port_ids_[circuit_model_id].size(); } @@ -404,8 +440,7 @@ CircuitModelId CircuitLibrary::add_circuit_model() { edge_src_pin_ids_.emplace_back(); edge_sink_port_ids_.emplace_back(); edge_sink_pin_ids_.emplace_back(); - edge_trise_.emplace_back(); - edge_tfall_.emplace_back(); + edge_timing_info_.emplace_back(); /* Delay information */ delay_types_.emplace_back(); @@ -1307,6 +1342,7 @@ void CircuitLibrary::build_timing_graphs() { invalidate_circuit_model_timing_graph(circuit_model_id); build_circuit_model_timing_graph(circuit_model_id); /* Annotate timing information */ + set_timing_graph_delays(circuit_model_id); } return; } @@ -1351,8 +1387,8 @@ void CircuitLibrary::add_edge(const CircuitModelId& circuit_model_id, edge_sink_pin_ids_[circuit_model_id].push_back(to_pin); /* Give a default value for timing values */ - edge_trise_[circuit_model_id].push_back(0); - edge_tfall_[circuit_model_id].push_back(0); + std::vector timing_info(2, 0); + edge_timing_info_[circuit_model_id].emplace_back(timing_info); return; } @@ -1361,7 +1397,7 @@ void CircuitLibrary::set_edge_trise(const CircuitModelId& circuit_model_id, cons /* validate the circuit_edge_id */ VTR_ASSERT_SAFE(valid_circuit_edge_id(circuit_model_id, circuit_edge_id)); - edge_trise_[circuit_model_id][circuit_edge_id] = trise; + edge_timing_info_[circuit_model_id][circuit_edge_id][size_t(SPICE_MODEL_DELAY_RISE)] = trise; return; } @@ -1369,10 +1405,76 @@ void CircuitLibrary::set_edge_tfall(const CircuitModelId& circuit_model_id, cons /* validate the circuit_edge_id */ VTR_ASSERT_SAFE(valid_circuit_edge_id(circuit_model_id, circuit_edge_id)); - edge_tfall_[circuit_model_id][circuit_edge_id] = tfall; + edge_timing_info_[circuit_model_id][circuit_edge_id][size_t(SPICE_MODEL_DELAY_FALL)] = tfall; return; } +/* Decode input names of delay_info to CircuitPorts */ +std::vector CircuitLibrary::get_delay_info_input_port_ids(const CircuitModelId& circuit_model_id, + const enum spice_model_delay_type& delay_type) const { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + /* Parse the string */ +// MultiPortParser input_port_parser(delay_in_port_names[circuit_model_id][size_t(delay_type)]); +// input_port_parser.add_delima(" "); +// std::vector input_port_names = input_port_parser.port_names(); + + /* Find port ids with given names */ + std::vector input_port_ids; +// for (const auto& name : input_port_names) { + /* We must have a valid port ! */ +// VTR_ASSERT_SAFE(CIRCUIT_PORT_OPEN_ID != port(circuit_model_id, name)); + /* Convert to CircuitPortId */ +// input_port_ids.push_back(port(circuit_model_id, name)); + /* This must be an input port! */ +// VTR_ASSERT_SAFE(true == is_input_port(circuit_model_id, input_port_ids.back())); +// } + return input_port_ids; +} + +/* Decode input names of delay_info to CircuitPorts */ +std::vector CircuitLibrary::get_delay_info_output_port_ids(const CircuitModelId& circuit_model_id, + const enum spice_model_delay_type& delay_type) const { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + /* Parse the string */ +// MultiPortParser output_port_parser(delay_out_port_names[circuit_model_id][size_t(delay_type)]); +// output_port_parser.add_delima(" "); +// std::vector output_port_names = output_port_parser.port_names(); + + /* Find port ids with given names */ + std::vector output_port_ids; +// for (const auto& name : output_port_names) { + /* We must have a valid port ! */ +// VTR_ASSERT_SAFE(CIRCUIT_PORT_OPEN_ID != port(circuit_model_id, name)); + /* Convert to CircuitPortId */ +// output_port_ids.push_back(port(circuit_model_id, name)); + /* This must be an output port! */ +// VTR_ASSERT_SAFE(true == is_output_port(circuit_model_id, output_port_ids.back())); +// } + return output_port_ids; +} + + +/* Annotate delay values on a timing graph */ +void CircuitLibrary::set_timing_graph_delays(const CircuitModelId& circuit_model_id) { + /* validate the circuit_model_id */ + VTR_ASSERT_SAFE(valid_circuit_model_id(circuit_model_id)); + /* Go one delay_info by another */ + for (size_t i_delay_type = 0; i_delay_type < delay_types_[circuit_model_id].size(); ++i_delay_type) { + /* Parse the input port names and output names. + * We will store the parsing results in vectors: + * 1. vector for port ids for each port name + * 2. vector for pin ids for each port name + */ + std::vector input_port_ids; + std::vector input_pin_ids; + + std::vector output_port_ids; + std::vector output_pin_ids; + } + return; +} /************************************************************************ * Internal mutators: build fast look-ups @@ -1481,8 +1583,7 @@ void CircuitLibrary::invalidate_circuit_model_timing_graph(const CircuitModelId& edge_sink_port_ids_[circuit_model_id].clear(); edge_sink_pin_ids_[circuit_model_id].clear(); - edge_trise_[circuit_model_id].clear(); - edge_tfall_[circuit_model_id].clear(); + edge_timing_info_[circuit_model_id].clear(); return; } diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h index 04c220876..72300d4e1 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/circuit_library.h @@ -237,6 +237,9 @@ class CircuitLibrary { bool is_output_buffered(const CircuitModelId& circuit_model_id) const; bool is_lut_intermediate_buffered(const CircuitModelId& circuit_model_id) const; public: /* Public Accessors: Basic data query on Circuit Ports*/ + bool is_input_port(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; + bool is_output_port(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; + CircuitPortId port(const CircuitModelId& circuit_model_id, const std::string& name) const; size_t num_ports(const CircuitModelId& circuit_model_id) const; enum e_spice_model_port_type port_type(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; size_t port_size(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; @@ -428,6 +431,11 @@ class CircuitLibrary { const CircuitPortId& to_port, const size_t& to_pin); void set_edge_trise(const CircuitModelId& circuit_model_id, const CircuitEdgeId& circuit_edge_id, const float& trise); void set_edge_tfall(const CircuitModelId& circuit_model_id, const CircuitEdgeId& circuit_edge_id, const float& tfall); + std::vector get_delay_info_input_port_ids(const CircuitModelId& circuit_model_id, + const enum spice_model_delay_type& delay_type) const; + std::vector get_delay_info_output_port_ids(const CircuitModelId& circuit_model_id, + const enum spice_model_delay_type& delay_type) const; + void set_timing_graph_delays(const CircuitModelId& circuit_model_id); public: /* Internal mutators: build fast look-ups */ void build_circuit_model_lookup(); void build_circuit_model_port_lookup(const CircuitModelId& circuit_model_id); @@ -509,8 +517,7 @@ class CircuitLibrary { vtr::vector> edge_src_pin_ids_; vtr::vector> edge_sink_port_ids_; vtr::vector> edge_sink_pin_ids_; - vtr::vector> edge_trise_; - vtr::vector> edge_tfall_; + vtr::vector>> edge_timing_info_; /* x0 => trise, x1 => tfall */ /* Delay information */ vtr::vector> delay_types_;